Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

Strano, Alessandro; Gómez, C.; Ludovici, Daniele; Favalli, M.; Gómez, María E.; Bertozzi, Davide

doi:10.1109/date.2011.5763109

Cited by 39 publications

(14 citation statements)

References 17 publications

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“…Finally, a cooperative framework is devised in order to cover also the TPG faults, such that each switch tests the block instances of its neighboring switches. In this scheme, switches exchange test patterns and/or test responses with each other [4].…”

Section: Design Methodsmentioning

confidence: 99%

Quest for the ultimate network-on-chip

Strano

Bertozzi

Angiolini³

et al. 2012

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop

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The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networkson-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future systems like virtualization, power, thermal and application management, as well as new challenges in technology scaling like reliability and variability. The introduction of networks-on-chip into the platform enables a component-oriented architectural design which is out of reach of current design methods. This paper presents an overview of the achievements at the end of the second out of three years of planned activities.

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Section: Design Methodsmentioning

confidence: 99%

Quest for the ultimate network-on-chip

Strano

Bertozzi

Angiolini³

et al. 2012

Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop

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“…In [20] an NoC with a faulty router or a broken link is repaired using spare routers. The inherent structural redundancy of the NoC architecture is exploited in a cooperative way to detect the faults using BIST [21]. Also diagnosis units in switches are utilized to localize a fault.…”

Section: Related Workmentioning

confidence: 99%

Transaction-based online debug for NoC-based multiprocessor SoCs

Dehbashi

Fey

2015

Microprocessors and Microsystems

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a b s t r a c tAs complexity and size of Systems-on-Chip (SoC) grow, debugging becomes a bottleneck for designing IC products. In this paper, we present an approach for online debug of NoC-based multiprocessor SoCs. Our approach utilizes monitors and filters implemented in hardware. Monitors and filters observe and filter transactions at run-time. They are connected to a Debug Unit (DU). Transaction-based programmable Finite State Machines (FSMs) in the DU check assertions online to validate the correct relation of transactions at run-time. The experimental results show efficiency and performance of our approach.

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“…The concept of exploration/scouting packets [Puente et al 2008] has been employed to identify faulty nodes ahead of regular data packets. Similar to scouting packets, a common method used for fault detection is the broadcasting of test vectors, either during boot-up [Strano et al 2011;Hosseinabady et al 2007] or at runtime. In order to mitigate the performance degradation caused by testing interruptions, token-based mechanisms have been explored [Kakoee et al 2011a[Kakoee et al , 2014 as well as hardware for monitoring specific modules, such as the router arbiters or datapath components [Seitanidis et al 2014].…”

Section: Detection/localizationmentioning

confidence: 99%

“…Traditionally, fault detection is undertaken by Built-In Self-Test (BIST) mechanisms. The BIST process may be executed by the manufacturer prior to shipment, or it may constitute part of system boot-up [Strano et al 2011;Hosseinabady et al 2007]. Runtime BIST is also possible, but system operation is (partially) halted while the module under test is examined [Fick et al 2009b;Kakoee et al 2011a].…”

Section: Introductionmentioning

confidence: 99%

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Chrysanthou

Englezakis

Prodromou

et al. 2016

ACM Trans. Archit. Code Optim.

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Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose NoCAlert, a comprehensive online and real-time fault detection and localization mechanism that demonstrates 0% false negatives within the interconnect for the fault models and stimulus set used in this study. Based on the concept of invariance checking, NoCAlert employs a group of lightweight microchecker modules that collectively implement real-time hardware assertions. The checkers operate concurrently with normal NoC operation, thus eliminating the need for periodic, or triggered-based, self-testing. Based on the pattern/signature of asserted checkers, NoCAlert can pinpoint the location of the fault at various granularity levels. Most important, 97% of the transient and 90% of the permanent faults are detected instantaneously, within a single clock cycle upon fault manifestation. The fault localization accuracy ranges from 90% to 100%, depending on the desired localization granularity. Extensive cycle-accurate simulations in a 64-node CMP and analysis at the RTL netlist-level demonstrate the efficacy of the proposed technique.

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Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

Cited by 39 publications

References 17 publications

Quest for the ultimate network-on-chip

Quest for the ultimate network-on-chip

Transaction-based online debug for NoC-based multiprocessor SoCs

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

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