Exploiting pipelining to relax register-file port constraints of instruction-set extensions

A high-level synthesis flow for custom instruction set extensions for application-specific processors

“…The first step of the flow determines the minimum latency of each ISE given the I/O constraints of the processor's register file [15,17]. The following step reschedules each ISE in order to reduce area, without increasing its latency.…”

“…Our target processor is a RISC with R = 2 read ports and W = 1 write ports. We identify ISEs having up to 5 inputs and 2 outputs [15]. Our benchmarks are cryptography, signal processing, and multimedia applications taken from established suites.…”

“…We assume that the target processor has a frequency of 1/Λ = 200 MHz. Using the method of Pozzi and Ienne [15], we searched for ISEs having up to 5 inputs and 2 outputs; as the processor has R = 2 read ports and W = 1 write ports, the largest ISEs found had to be serialized to form multi-cycle ISEs. We considered four different synthesis flows: …”

“…Extensible processors allow the user to augment a base processor, typically an in-order RISC or VLIW, with application specific custom instruction set extensions (ISEs) [4,[13][14][15]17]. ISEs may be realized in ASIC technology, along with the processor, or synthesized on a closely-coupled reconfigurable datapath.…”

“…The first step of the flow is to compute a minimum latency schedule for each ISE given the I/O constraints of the processor [15,17]. The second step of the flow reschedules each ISE to reduce a coarse-grain estimate of the resource requirements; the scheduler ensures that the critical path is not violated and that the latency of the schedule does not increase.…”