Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems

Abstract

The write performance of flash memory has been degraded significantly due to the recent density-oriented advancements of flash technology. Techniques have been proposed to improve the write performance by exploiting the varying strength of a flash block in its different worn-out stages. A block is written with a faster speed when it is new and strong, and gradually will be written with slower speeds as it is aging and becomes weak. Motivated by these works, this brief proposes a new technique by exploiting the significant process variation among flash blocks introduced by the advanced technology scaling. First, a write speed detection approach is proposed to identify the strength of each block. Then, a heuristic approach is proposed to exploit the speed variation among blocks for write performance improvement. A series of trace-driven simulations shows that the proposed approach generates substantial write performance improvement over state-of-the-art approaches by 30% on average.

RT-ROS: A real-time ROS architecture on multi-core processors

“…For example, the angular velocity or electric current based method can be adopted to get a more accurate synchronous motion control. Moreover, many emerging memory and storage techniques have been proposed [28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47]. We will study how to utilize them to further optimize the performance of RT-ROS.…”

Error source and latency-aware read performance optimization scheme for aged SSDs

“…The figure 3 [16,17], recording RL at block level may induce to erroneous RL recording, even it saves memory overhead. In our design, we apply the RL recording at the page level for planner NAND flash and layer level for 3D NAND flash, respectively.…”

VIOS: A Variation-Aware I/O Scheduler for Flash-Based Storage Systems

“…Therefore, with the awareness of both process variation and the BERspeed relationship, write speed for lower-BER blocks can be increased at the cost of reduced noise margins, while that for higher-BER blocks should be carefully optimized without exceeding the capability of the deployed ECC. The challenge to detect the proper write speed for each block at its current worn out state is also solved by periodically reading out the written data to find out the number of faulty bits, and the analysis indicates that overhead is negligible [13]. In this paper, the blocks of each chip are sorted according to their detected write speeds and conflict write requests are allocated to faster blocks to reduce access conflict of waiting requests.…”

“…Woo et al [12] introduced a new measure that predicts the remaining lifetime of a flash block more accurately than the erase count based on the findings that all the flash blocks could survive much longer than the guaranteed numbers and the number of P/E cycles varies significantly among blocks. Shi et al [13] further exploited the process variation by detecting supported write speeds during the lifetime of each flash block and allocating blocks in a way that hotter data are matched with faster blocks, but they did not reorder the requests in the I/O scheduling layer. Therefore, none of these works focuses on incorporating the awareness of inter-block variation into I/O scheduling to minimize the access conflict latency of I/O requests.…”