Exploiting Resonant Behavior to Reduce Inductive Noise

Abstract

Inductive noise in high-performance microprocessors is a reliability issue caused by variations in processor current (di/dt) which are converted to supply-voltage glitches by impedances in the power-supply network. Inductive noise has been addressed by using decoupling capacitors to maintain low impedance in the power supply over a wide range of frequencies. However, even well-designed power supplies exhibit (a few) peaks of high impedance at resonant frequencies caused by RLC resonant loops. Previous architectural proposals adjust current variations by controlling instruction fetch and issue, trading off performance and energy for noise reduction. However, the proposals do not consider some conceptual issues and have implementation challenges. The issues include requiring fast response, responding to variations that do not threaten the noise margins, or responding to variations only at the resonant frequency while the range of high impedance extends to a resonance band around the resonant frequency. While previous schemes reduce the magnitude of variations, our proposal, called resonance tuning, changes the frequency of current variations away from the resonance band to a non-resonant frequency to be absorbed by the power supply. Because inductive noise is a resonance problem, resonance tuning reacts only to repeated variations in the resonance band, and not to isolated variations. Reacting after a few repetitions allows more time for the response and reduces unnecessary responses, decreasing performance and energy loss.

Architecture implications of pads as a scarce resource

“…They either use lumped PDN models that collapse all pads into a single resistor-inductor pair [8,10,30], or use coarse-grained models that are not able to accurately capture the effect of pad count and location [9]. Fig.…”

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation

“…Several publications [Grochowski et al 2002;Joseph et al 2004;Powell and Vijaykumar 2004] have proposed hardware-based microarchitectural solutions as well as hybrid hardware/software techniques [Hazelwood and Brooks 2004]. Different from the preceding, mentioned work tackling the mid-frequency dI/dt issue (50-100HMz), the focus of this article is to mitigate high-frequency dI/dt that requires immediate response, for which the solutions just mentioned are inappropriate.…”

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

“…Interest in microarchitectural support has grown due to the increasing difficulty of mitigating noise through conventional avenues [18]- [20]. Traditionally, inductive noise could be addressed by reducing effective inductance or adding capacitance on-die or in the package to dampen out the noise.…”