Exploiting structure of wafer distortion in global alignment

Abstract

One of the most critical emerging challenges in lithography is achieving rapid and accurate alignment. The problem is exacerbated by wafer and stage distortions. Thus, an effective learning process is needed to rapidly acquire the best possible positional information from an array of marks across the wafer. An algorithm based on a neural network model of global alignment was presented [A. A. Ghazanfarian et al., Proc. SPIE 3051, 629 (1997); J. Vac. Sci. Technol. B 15, 2146 (1997)], which incorporated both wafer and stage distortion. Yet in almost all cases, the stepper machines are precalibrated and the stage distortion is well controlled. Therefore, the aforementioned methods need to be revisited to specifically address the wafer distortion problem. In this article, we propose a new global alignment algorithm based on array processing techniques [J. Rissanen et al., Automatica 14, 465 (1978); M. Wax et al., IEEE Trans. Acoust., Speech, Signal Process], which exploits the structure of the overlay data from prior wafers to characterize the wafer distortion for a new wafer. The algorithm has been applied to overlay data from Advanced Micro Devices, Inc., Overlay error has been measured on 9(3×3) sites, with five measurements per site. We have used data for two pairs of lots, each pair belonging to the same process. The model obtained from the first lot of each pair is used in global alignment of the wafers in the second lot. Results indicate more than 70% improvement in alignment accuracy compared to the current global alignment algorithm, with the average error reduced by about 30 nm. It is also faster than the site-by-site alignment algorithm; simulation results from a bowing distortion example show that the proposed algorithm requires measurement from only six sites.