Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Wu, Guanying; He, Xubin; Xie, Ningde; Zhang, Tong

doi:10.1145/2489792

Cited by 15 publications

(5 citation statements)

References 38 publications

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“…In addition, a small sized code word can be helpful to reduce the read latency. 24 As a result, the segment length of BCH codes in real-world SSD is usually smaller than the page size, for example, 0.5KiB ∼ 4KiB 25,26 vs 2KiB ∼ 16KiB. 8,27 In other words, to use BCH codes, a page of which the size is larger than 4KiB can be first divided into several small sized segments.…”

Section: Raw Bit Errors and In-page Eccsmentioning

confidence: 99%

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Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

Zhou

Tan

et al. 2020

Concurrency and Computation

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Summary Solid state drives (SSDs) built upon MLC NAND flash memories suffer from a low lifetime endurance induced by continuously scaling‐down feature sizes and increasing bit density per cell. To cost‐effectively address this problem, we propose to integrate both hierarchical data redundancy and heterogeneous flash memory techniques into the SSD, named H2‐SSD. Through deploying across‐chips data redundancy in addition to conventional in‐page error correction codes, error correction capacity, so does the lifetime endurance of H2‐SSD can be dramatically improved. Furthermore, an extra small‐size sisngle‐level cell (SLC) chip is integrated into H2‐SSD to store across‐chips parities. Due to the high program/erase performance and lifetime endurance of that SLC chip, I/O performance degradation induced by the hierarchical data redundancy can be significantly mitigated, even under strict synchronous parity update strategies. Quantitative analysis and trace‐driven simulations are conducted to evaluate the effectiveness and efficiency of H2‐SSD, in both the scenes with and without degraded reads. Experimental results demonstrate that H2‐SSD outperform the conventional SSD in maximum Program/Erase cycles by 23% to 178%, and suffer from negligible degradation of I/O performance in terms of both throughput and average response time in most cases.

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Section: Raw Bit Errors and In-page Eccsmentioning

confidence: 99%

“…In addition, a small sized code word can be helpful to reduce the read latency 24 . As a result, the segment length of BCH codes in real‐world SSD is usually smaller than the page size, for example, 0.5KiB ∼ 4KiB 25,26 vs 2KiB ∼ 16KiB 8,27 .…”

Section: Background and Related Workmentioning

confidence: 99%

Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

Zhou

Tan

et al. 2020

Concurrency and Computation

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“…There is also much research on the architectures of solid state drives (SSDs) [Payer et al 2009;Seong et al 2010;Sun et al 2010;Chang and Wen 2014;Chang et al 2014b;Wu et al 2013]. These works mainly focus on the optimization of parallel read or write without considering the garbage collection in SSDs.…”

Section: Related Workmentioning

confidence: 99%

Lazy-RTGC

Zhang

Wang

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Due to many attractive and unique properties, NAND flash memory has been widely adopted in missioncritical hard real-time systems and some soft real-time systems. However, the nondeterministic garbage collection operation in NAND flash memory makes it difficult to predict the system response time of each data request. This article presents Lazy-RTGC, a real-time lazy garbage collection mechanism for NAND flash memory storage systems. Lazy-RTGC adopts two design optimization techniques: on-demand page-level address mappings, and partial garbage collection. On-demand page-level address mappings can achieve high performance of address translation and can effectively manage the flash space with the minimum RAM cost. On the other hand, partial garbage collection can provide the guaranteed system response time. By adopting these techniques, Lazy-RTGC jointly optimizes both the average and the worst system response time, and provides a lower bound of reclaimed free space. Lazy-RTGC is implemented in FlashSim and compared with representative real-time NAND flash memory management schemes. Experimental results show that our technique can significantly improve both the average and worst system performance with very low extra flash-space requirements. . 2015. Lazy-RTGC: A real-time lazy garbage collection mechanism with jointly optimizing average and worst performance for NAND flash memory storage systems.

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“…For each write request, FTL will handle the write request and allocate a physical page. It will search and update the mapping table stored in RAM or in flash (Lines [15][16][17][18]. Based on the mapping information, FTL will issue write operations to the MTD layer, and the MTD layer will write or update data in the flash memory chip (Line 19).…”

Section: Metadata Transparent Replicationmentioning

confidence: 99%

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

Wang

Huang

Shao

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibit errors. NAND flash memory is normally used to store the file system metadata and page mapping information. Thus, a broken physical page containing metadata may cause an unintended and severe change in functionality of the entire flash. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multibit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. We evaluate Meta-Cure under a real-embedded platform using a variety of I/O traces. The evaluation platform adopts dual ARM Cortex A9 processor cores with 64 Gb NAND flash memory. We have evaluated the effectiveness of Meta-Cure on the new technology file system file system. Experimental results show that the proposed technique can reduce uncorrectable page errors by 70.38% with less than 7.86% time overhead in comparison with conventional error correction techniques.

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Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes

Cited by 15 publications

References 38 publications

Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

Cost‐effectively improving solid state drive lifetime by hierarchical redundancy and heterogeneous memories

Lazy-RTGC

A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems

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