2023
DOI: 10.1088/1402-4896/acd9fc
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Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Parabi Datta,
Swagat Nanda,
Rudra Sankar Dhar

Abstract: With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-… Show more

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