Exploration of multilayer field-coupled nanomagnetic circuits

Santoro, Giulia; Vacca, Marco; Bollo, Matteo; Riente, Fabrizio; Graziano, Mariagrazia; Zamboni, Maurizio

doi:10.1016/j.mejo.2018.06.014

Cited by 7 publications

(4 citation statements)

References 16 publications

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“…The results show remarkable improvements in comparison with the recent proposed MUXs (Bhoi et al, 2018;Santoro et al, 2018). In future works, it is suggested to apply other mechanisms and layout to reduce power dissipation in CLKs which are the most important components of the total power consumption in NML devices.…”

Section: Discussionmentioning

confidence: 73%

“…The spacing between two ferromagnetic and anti-ferromagnetic nanomagnets is 24 nm and 10 nm, respectively, since the ferromagnetic coupling is stronger than the anti-ferromagnetic one (Csaba et al, 2013) and these values result in equilibrium between coupling energies (Soares et al, 2018). Both 2:1 and 4:1 structures have five layers with 20 nm vertical space between two adjacent layers (Santoro et al, 2018).…”

Section: Proposed 2:1 and 4:1 Multiplexersmentioning

confidence: 99%

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Novel implementation of 3D multiplexers in nano magnetic logic technology

Farzaneh

Mirzaee

Navi

2020

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Purpose Owing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology. Design/methodology/approach The proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations. Findings The results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved. Originality/value These findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare.

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Section: Discussionmentioning

confidence: 73%

Section: Proposed 2:1 and 4:1 Multiplexersmentioning

confidence: 99%

Novel implementation of 3D multiplexers in nano magnetic logic technology

Farzaneh

Mirzaee

Navi

2020

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“…Some particular elements were necessary to design the fulladder. From a nanomagnet at the output of the first XOR to a nanomagnet at the wire below the Cin wire, the vertical black line is an NMLSim feature that simulates a multilayer information crossing [15]. The left inset presents a simple and easy to implement fan-out, copying the carry-in value to the second XOR gate and the upper AND gate.…”

Section: Resultsmentioning

confidence: 99%

NMLib: A Nanomagnetic Logic Standard Cell Library

Luz

Nacif

Ferreira

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The Nanomagnetic Logic (NML) is a promising new technology that can build low-power devices at room temperature. Furthermore, this technology allows mixing logic and memory on the same device. The creation of Electronic Design Automation (EDA) tools and flows is an essential step towards developing NML for integrated designs. There is plenty of room for creating new EDA methodologies for this kind of emerging nanotechnologies since the scarce number of works in this field. Standard cells is an important step in this context since they strongly relate to the routing and placement algorithms. This work presents NMLib, an NML cell library developed for the NMLSim 2.0 simulator. In contrast to CMOS, the NML features require logic cells and interconnection cells, since all circuit is developed using the same building block. Moreover, we present a full-adder, and a ripple carry adder circuit designs using NMLib to demonstrate NMLib feasibility.

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“…Moreover, pNML technology allows one to build 3D structures by stacking different layers of nanomagnets [44,45,46,47]. Previous works such as [42,48,49,50,51,52] already explore the potentialities of NanoMagnetic Logic architectures (3D and non), but none of them propose a complete Logic-in-Memory design, which is instead presented in the following.…”

Section: Beyond Cmos: a Pnml Implementationmentioning

confidence: 99%

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

2019

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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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Exploration of multilayer field-coupled nanomagnetic circuits

Cited by 7 publications

References 16 publications

Novel implementation of 3D multiplexers in nano magnetic logic technology

Novel implementation of 3D multiplexers in nano magnetic logic technology

NMLib: A Nanomagnetic Logic Standard Cell Library

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

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