Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

Abstract

SRAM-based fingerprinting uses deviations in power-up behaviour caused by the CMOS fabrication process to identify distinct devices. This method is a promising technique for unique identification of physical devices. In the case of SRAM-based hardware reconfigurable devices such as FPGAs, the integrated SRAM cells are often initialized automatically at power-up, sweeping potential identification data. We demonstrate an approach to utilize unused parts of configuration memory space for device identification. Based on a total of over 200,000 measurements on nine Xilinx Virtex-5 FPGAs, we show that the retrieved values have promising properties with respect to consistency on one device, variety between different devices, and stability considering temperature variation and aging.

Analysis and Evaluation of PUF-Based SoC Designs for Security Applications

“…Experiments regarding the SRAM PUF are presented in [1] but this PUF suffers from two main drawbacks: i) the SRAM PUF is not available on all mainstream FPGA platforms (because no uninitialized SRAM is available on most types) [23]; nowadays, most of the FPGA manufacturers reset the start-up state of the SRAM cells to a known value, rendering the SRAM-PUF difficult to be used [17,18]; ii) the response of the SRAM PUF is generated only on the power-up state of the circuit, the output of the PUF circuit could not be regenerated while the circuit is operational [16]. The authors of [17] attempt to remove the fundamental obstacle Xilinx FPGAs havefrom the SRAM-PUF point of view -by using a work-around that enables to disconnect uninstantiated BRAM from the power supply network. The complex mechanism is based on 3 partial reconfigurations and the results regarding the uniqueness are not successful.…”

Enabling SRAM-PUFs on Xilinx FPGAs

“…The straightforward design of Static Random-Access Memory (SRAM)-based PUFs which simply evaluate initial states of memory cells have been identified as promising and have already been emerged to IP cores for integration into ASICs. However, transferring this concept to Field Programmable Gate Arrays (FPGAs) -at least for those of the market leader Xilinx -is not possible since all SRAM-based block memories (BRAM) in Xilinx FPGAs are automatically cleared on power-up [10], destroying the desired initial information bits. Due to this startup procedure, it is therefore widely assumed that it is not possible to implement SRAM-PUFs in Xilinx FPGAs.…”