Exploring area and total wirelength using a cell merging technique

Albinagorta, Kevin A. Caceres; Conceicao, Calebe; Cardenas, Carlos Silva; Reis, Ricardo

doi:10.1109/vlsi-soc.2019.8920337

Cited by 4 publications

(2 citation statements)

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“…Other authors claim that this semi-custom technique may result in a less efficient implementation of the circuit as the designer is limited to the technology library. Merging logic gates or using a libraryfree design could further optimize the results obtained during the logic synthesis [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…Recent developments in EDA tools, presented in [7,8], show a standard cell-like approach, in which the logic synthesis is optimized for a much larger set of logic functions, and the gates for each one are designed automatically according to the designer's need. This library-free design technique also referred to as design on-the-fly in this paper, enables the use of complex gates, minimizing the number of transistors and the average length of wires.…”

Section: Introductionmentioning

confidence: 99%

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Electrical Evaluation of Logic Network Generation Methods for On-the-Fly Supergate Design

Kessler

Muñoz

Finkenauer

et al. 2021

JICS

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Recent developments in electronic design automation tools vastly reduce the design cost of supergates, enabling an alternative approach to logic synthesis. Despite many design strategies targeting the transistors network in supergates, their comparisons are often limited to metrics such as the number of transistors used or circuit total stack, lacking an in-depth electrical evaluation. This work presents an electrical comparison of three different design techniques. The study evaluates the 3,982 logic functions of the 4 input P-class, and it shows that topologies that optimize both pull-up and pull-down networks individually presented better overall electrical characteristics. The results also suggest that reducing the logic gate stack or the number of transistors does not necessarily lead to better performance. Additionally, the results show that a single network generation method can yield in a comparatively good design or in a supergate that could achieve 50% smaller propagation delay and power dissipation by another approach, pointing to a strong dependency between the effectiveness of the method and the logic function being implemented.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%