Exploring CAM Design For Network Processing Using FPGA Technology

McLaughlin, Kieran; O’Connor, Nessa E.; Sezer, Sakir

doi:10.1109/aict-iciw.2006.96

Cited by 12 publications

(7 citation statements)

References 8 publications

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“…There are several methods of implementing CAM functionality on FPGAs [30]. CAMs implemented in soft logic use registers for storage and LUTs to read, write, and search the stored bits.…”

Section: Content-addressable Memoriesmentioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

102

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As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates. We then use the results of these comparisons to infer how the microarchitecture of soft processors on FPGAs should be different from hard processors on custom CMOS.We find that the ratios of the area required by an FPGA to that of custom CMOS for different building blocks varies significantly more than the speed ratios. As area is often a key design constraint in FPGA circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores have area ratios of 17-27× and delay ratios of 18-26×. Building blocks that have dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7× area ratio), while multiplexers and CAMs are particularly area-inefficient (> 100× area ratio), leading to cheaper ALUs, larger caches of low associativity, and more expensive bypass networks than on similar hard processors. We also find that a low delay ratio for pipeline latches (12-19×) suggests soft processors should have pipeline depths 20% greater than hard processors of similar complexity.

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“…There are several methods of implementing CAM functionality on FPGAs [30]. CAMs implemented in soft logic use registers for storage and LUTs to read, write, and search the stored bits.…”

Section: Content-addressable Memoriesmentioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

102

View full text Add to dashboard Cite

show abstract

“…On the other side, writing a new entry or deleting one is much more involved operations that require several steps. In [21] a number of CAM designs suitable for FPGA implementation are discussed. Our approach is a RAM-based design (in terms of resources used) but with a significant difference in the interpretation of the RAM ports semantics, as explained in [6].…”

Section: Hardware Tlb Implementationmentioning

confidence: 99%

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces

Ammendola

Biagioni

Frezza

et al. 2015

Future Generation Computer Systems

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“…In [13] a number of CAM designs suitable for FPGA implementation are discussed. Our approach is a RAM-based design (in terms of resources used) but with a significant difference in the interpretation of the RAM ports semantics.…”

Section: ) Buffer Searchmentioning

confidence: 99%

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

Ammendola

Biagioni²,

Frezza³

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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We developed a custom FPGA-based Network Interface Controller named APEnet+ aimed at GPU accelerated clusters for High Performance Computing. The card exploits peer-to-peer capabilities (GPU-Direct RDMA) for latest NVIDIA GPGPU devices and the RDMA paradigm to perform fast direct communication between computing nodes, offloading the host CPU from network tasks execution. In this work we focus on the implementation of a Virtual to Physical address translation mechanism, using the FPGA embedded soft-processor. Address management is the most demanding task -we estimated up to 70% of the µC load -for the NIC receiving side, resulting being the main culprit for data bottleneck. To improve the performance of this task and hence improve data transfer over the network, we added a specialized hardware logic block acting as a Translation Lookaside Buffer. This block makes use of a peculiar Content Address Memory implementation designed for scalability and speed. We present detailed measurements to demonstrate the benefits coming from the introduction of such custom logic: a substantial address translation latency reduction (from a measured value of 1.9 µs to 124 ns) and a performance enhancement of both host-bound and GPU-bound data transfers (up to ∼ 60% of bandwidth increase) in given message size ranges.

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Exploring CAM Design For Network Processing Using FPGA Technology

Cited by 12 publications

References 8 publications

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces

Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities

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