Exploring FPGAs capability to host a HPC design

Foucher, Clément; Muller, Fabrice; Giulieri, A.

doi:10.1109/norchip.2010.5669494

“…An example of this approach can be found in the Erlangen Slot Machine [50,51] architecture, where adjacent modules utilize external Static Random-Access Memory (SRAM) interfaces for communication purposes. Likewise, [106] presents an architecture where functional units communicate via a multi-port memory controller, as well as a dedicated mail-box system for short messages.…”

Section: Additional Communication Architecturesmentioning

confidence: 99%

“…The most popular method of undertaking configuration activities, particularly in self-reconfigurable systems, is through the use of a sequential, instruction-based processor acting as the control mechanism; this processor will either interact directly with the on-chip configuration interface, or it will rely on a secondary dedicated circuit, aimed at accelerating the process. This approach has been applied in architectures and systems aimed at general computing [70,71,72,52,74,75], MPSoCs [109,110,111,112,113], High-Performance Computing (HPC) [106,80] and video and multimedia-oriented systems [76,114,53,56,77,78,104,105,99,115]. In these architectures, the configuration controller is integrated on-chip with the rest of the system; thus, the FPGA device used can self-reconfigure.…”

Section: Configuration Controlmentioning

confidence: 99%

“…To obtain a better understanding of why this drastic difference occurs, Figure 8.7 shows the The second approach to control system implementation is the use of a central, sequential instruction-based programmable processor. As already stated, a large number of research works rely on this approach to configuration, link establishment and scheduling, whether they be general computing systems [52,51,110,75], high-performance computing systems [106,80], or dedicated multimedia processors [76,56,77,78,104,105,99]. Thus, a comparison is conducted between these two approaches to system control design.…”

Section: Control System Performance and Resource Cost Analysismentioning

confidence: 99%

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A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

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A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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“…An example of this approach can be found in the Erlangen Slot Machine [50,51] architecture, where adjacent modules utilize external Static Random-Access Memory (SRAM) interfaces for communication purposes. Likewise, [106] presents an architecture where functional units communicate via a multi-port memory controller, as well as a dedicated mail-box system for short messages.…”

Section: Additional Communication Architecturesmentioning

confidence: 99%

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Dumitriu¹

2023

Preprint

0

View full text Add to dashboard Cite

A number of modern digital processing systems implement complex multi-mode applications with high performance requirements and strict operating constraints; examples include video processing and telecommunication applications. A number of these systems use increasingly large FPGAs as the implementation medium, due to reduced development costs. The combination of increases in FPGA capacity and system complexity has lead to a non-linear increase in system implementation effort. If left unchecked, implementation effort for such systems will reach the point where it becomes a design and development bottleneck. At the same time, the reduction in transistor size used to manufacture these devices can lead to increased device fault rates. To address these two problems, the Multi-mode Adaptive Collaborative Reconfigurable self-Organized System (MACROS) Framework and design methodology is proposed and described in this work. The MACROS Framework other the ability for run-time architecture adaptation by integrating FPGA configuration into regular operation. The MACROS Framework allows for run-time generation of Application-Specific Processors (ASPs) through the deployment, assembly and integration of pre-built functional units; the framework further allows the relocation of functional units without affecting system functionality. The use of functional units as building blocks allows the system to be implemented on a piece-by-piece basis, which reduces the complexity of mapping, placement and routing tasks; the ability to relocate functional units allows fault mitigation by avoiding faulty regions in a device. The proposed framework has been used to implement multiple video processing systems which were used as verification and testing instruments. The MACROS framework was found to successfully support run-time architecture adaptation in the form of functional unit deployment and relocation in high performance systems. For large systems (more than 100 functional units), the MACROS Framework implementation effort, measured as time cost, was found to be one third that of a traditional (monolithic) system; more importantly, in MACRO Systems this time cost was found to increase linearly with system complexity (the number of functional units). When considering fault mitigation capabilities, the resource overhead associated with the MACROS Framework was found to be up to 85 % smaller than a traditional Triple Module Redundancy (TMR) solution.

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“…Before introducing reconfigurable hardware and other elements of our approach, we first needed to make a basic test: was the HPC architecture easily implementable on our test material? This architecture was first presented in [19].…”

Section: Software Hpc Platformmentioning

confidence: 99%

Online codesign on reconfigurable platform for parallel computing

Foucher¹,

Muller²,

Giulieri³

2013

Microprocessors and Microsystems

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International audienceReconfigurable hardware offers new ways of accelerating computing by implementing hardware accelerators at run time. In this article, we present an approach allowing a hardware/software codesign of applications in which implementation can be chosen at run time depending on available resources. We propose a platform supporting this flow and describe its different implementations used to prove the feasibility of our approach. This platform allows the underlying hardware to be virtualized in order to have a generic architecture that can be used to run applications. Partial dynamic reconfiguration is used over Xilinx Virtex 5 boards to enhance reconfiguration capabilities

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Exploring FPGAs capability to host a HPC design

Cited by 3 publications

References 6 publications

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

A framework and method for the run-time on-chip synthesis of multi-mode self-organized reconfigurable stream processors

Online codesign on reconfigurable platform for parallel computing

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