Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies

Abstract

To handle the demand for very large main memory, we are likely to use nonvolatile memory (NVM) as main memory. NVM main memory will have higher latency than DRAM. To cope with this, we advocate a less-deep cache hierarchy based on a large last-level, NVM cache. We develop a model that estimates average memory access time and power of a cache hierarchy. The model is based on captured application behavior, an analytical power and performance model, and circuit-level memory models such as CACTI and NVSim. We use the model to explore the cache hierarchy design space and present latency-power tradeoffs for memory intensive SPEC benchmarks and scientific applications. The results indicate that a flattened hierarchy lowers power and improves average memory access time.

VeloC: Towards High Performance Adaptive Asynchronous Checkpointing at Large Scale

“…Cache management for many-core processors and deep hierarchies have been explored in various contexts: locationawareness [2], latency-power trade-offs [3], locality-aware data access control [4], software-defined cache hierarchies [5]. However, the aspect of using cache hierarchies for multi-core nodes in the context of producer-consumer scenarios received relatively little attention in the literature.…”

Sensitivity Analysis for Time Dependent Problems: Optimal Checkpoint-Recompute HPC Workflows

“…Existing work has also considered NVRAM as a viable solution for I/O staging [18], [19]. For example, different research work [20], [21] compare different architectural alternatives, study the potential impact of NVRAM on the performance of deep memory hierarchies [22], and study the potential impact of hybrid DRAM and byte-addressable NVRAM on both performance and energy perspectives of scientific applications through simulation [23]. However, our work requires a comprehensive characterization of performance/energy trade-offs using different regeneration and configuration options to understand co-design choices at scale.…”

OFF2F: A New Object File Format for Virtual Memory Systems to Support Volatile/non-Volatile Memory-Mixed Environment

“…Poremba et al analyzed the effect of non-volatile and volatile memory instrument rate on performance and power consumption in high performance computing [8]. Yoon et al conducted research where they treated non-volatile memory as one part of a memory hierarchy [9]. Guo et al proposed a method of treating non-volatile memory as a language with various properties [10].…”