Exploring memory hierarchy with ArchC

Abstract

This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, programmable systems composed by processor and memories may be rapidly simulated making use of ArchC, an Architecture Description Language (ADL) based on SystemC. Initially designed to model processor architectures, ArchC was extended to support a more detailed description of the memory subsystem, allowing the design space exploration of the whole programmable system. As an example, it is shown an image processing application, running on a SPARC-V8 processor-based architecture, which had its memory organization adjusted to minimize cache misses.

The ArchC Architecture Description Language and Tools

“…The first two are well-known general purpose architectures, the third is one of the most used processor in embedded control applications, and the following are modern architectures largely used in embedded systems. The SPARC-V8 functional model has been used to develop and explore memory hierarchy simulation in ArchC, (14,15) by performing experiments to evaluate several cache and hierarchy configurations using multimedia applications. This was our first step toward extending ArchC modeling capabilities beyond processor architecture boundaries, enabling designers to simulate complete systems, like SoCs, based on ArchC descriptions of processors and memory hierarchies.…”

“…ArchC SystemC simulators may be used for memory hierarchy exploration (14,15) and have even been successfully connected to other SystemC IPs to compose more complex digital systems. Depending on commandline options that can be passed to acsim, the generated simulator can be instrumented with several features to help on architecture exploration, like simulation statistics collection, trace generation, co-verification interface, etc.…”

A Proposed Virtualization Technique to Enhance IT Services

“…Network Virtualization Technique [11] Network virtualization techniques can be leveraged in the networking infrastructure to achieve the same benefits obtained through server and storage virtualization. Moreover the network, especially in the data center, must also support this new dynamic environment where the computing and storage infrastructures are consolidated and virtualized, to meet new requirements (VM mobility, for example) and facilitate the delivery of IT services across heterogeneous network access technologies to multiple end user devices.…”

Modeling and simulating memory hierarchies in a platform-based design methodology

“…Figure 2 shows its architecture resources description (AC ARCH), exemplifying the cache declarations. A more detailed description of ArchC and its resources can be found in [1,6]. …”

“…According to the system requirements and constraints, the system modules are tuned toward the desired performance and cost. Able to capture the entire programmable system specification, ArchC [6] is presented as a promising architecture description language (ADL), ready to model the main features of the processor, as well as the memory subsystem. Over such a model, it is possible to map a software application, and the simulation of the software running on the architectural model can help the designer to evaluate its efficiency and to adjust the parameters that may impact on the overall performance and power consumption of the system [3].…”