Exploring MRAM Technologies for Energy Efficient Systems-On-Chip

Senni, Sophiane; Torres, Lionel; Sassatelli, Gilles; Gamatié, Abdoulaye; Mussard, Bruno

doi:10.1109/jetcas.2016.2547680

Cited by 28 publications

(17 citation statements)

References 51 publications

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“…Moreover, when using STT, a larger access transistor size is required, thus limiting the application density. Yet another challenge with scaling down using STT is that the thermal stability factor scales down linearly with the area and the increase in retention failures due to thermal instability results in unreliable operations [17]. STT-based applications also face problems when high write speed is required because the switching current of STT is inversely proportional to the write pulse width [17].…”

Section: Spin Transfer Torque (Stt)mentioning

confidence: 99%

“…Figure 2 outlines the VCMA-MTJ operational characterization. As the switching is performed through voltage, the increasing of the barrier thickness can decrease the parasitic conductance and so the effect of current-induced torques [17]. The energy barrier between the P and AP states can be reduced with the use of VCMA.…”

Section: Voltage-controlled Magnetic Anisotropy (Vcma)mentioning

confidence: 99%

“…With the SOT technique, three terminals are used to separate the write and read paths allowing for a symmetrical switching current between the MTJ states. With that, the possibility of a bit flip during the read operation is reduced, therefore increasing the read stability [17]. When a current crosses the non-magnetic layer, spins are accumulated and a torque switching is generated over the magnetization of the ferromagnetic layer.…”

Section: Spin-orbit Torque (Sot)mentioning

confidence: 99%

See 2 more Smart Citations

Magnetic Tunnel Junction Applications

Maciel

Marques

Naviner

et al. 2019

Sensors

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Spin-based devices can reduce energy leakage and thus increase energy efficiency. They have been seen as an approach to overcoming the constraints of CMOS downscaling, specifically, the Magnetic Tunnel Junction (MTJ) which has been the focus of much research in recent years. Its nonvolatility, scalability and low power consumption are highly attractive when applied in several components. This paper aims at providing a survey of a selection of MTJ applications such as memory and analog to digital converter, among others.

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Section: Spin Transfer Torque (Stt)mentioning

confidence: 99%

Section: Voltage-controlled Magnetic Anisotropy (Vcma)mentioning

confidence: 99%

Section: Spin-orbit Torque (Sot)mentioning

confidence: 99%

See 1 more Smart Citation

Magnetic Tunnel Junction Applications

Maciel

Marques

Naviner

et al. 2019

Sensors

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“…This is because the area of the cell array occupies a large proportion of the total memory area compared to the area of the peripheral circuitry [19].…”

Section: Area Analysismentioning

confidence: 99%

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

et al. 2017

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Since the advent of complementary metal oxide semiconductors (CMOS), the number of transistor per die never stops increasing to reach today several billion of transistors. As a result, design and fabrication of smart devices able to run at high speed has been possible. However, the power consumption of systems-on-chip has significantly increased due to the high density integration and the high leakage power of current CMOS transistors. As a result, a heat dissipation wall makes difficult further improvement in performance. Having high autonomy for battery-powered devices becomes a real challenge. To deal with these issues, STT-MRAM technology is seen as a promising solution. In addition to its attractive performance features, STT-MRAM can bring non-volatility inside a system to allow full data retention after a complete shutdown while keeping a fast wake-up time. Considering two 32-bit embedded processors, this paper shows how STT-MRAM can improve energy efficiency and reliability of future embedded systems thanks to normally-off computing and checkpointing/rollback techniques. Finally, a detailed analysis is performed to evaluate the cost related to the backup/recovery of the system. Index Terms-Spintronic memory and logic, embedded processor.

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“…This enables us to assess the synergistic impact of the multi-level design decisions on system performance and energy consumption. As in [3], we use the gem5 simulator [4] for performance evaluation, and NVSim [5] and McPAT [6] for estimating the energy respectively related to NVMs and the rest of the architecture.…”

Section: Introductionmentioning

confidence: 99%

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs

Péneau

Bouziane

Abdoulayse

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Energy-efficiency is one of the most challenging design issues in both embedded and high-performance computing domains. The aim is to reduce as much as possible the energy consumption of considered systems while providing them with the best computing performance. Finding an adequate solution to this problem certainly requires a cross-disciplinary approach capable of addressing the energy/performance trade-off at different system design levels. In this paper, we present an empirical impact analysis of the integration of Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) technologies in multicore architectures when applying some existing compiler optimizations. For that purpose, we use three well-established architecture and NVM evaluation tools: NVSim, gem5 and McPAT. Our results show that the integration of STT-MRAM at cache memory levels enables a significant reduction of the energy consumption (up to 24.2 % and 31 % on the considered multicore and monocore platforms respectively) while preserving the performance improvement provided by typical code optimizations. We also identify how the choice of the clock frequency impacts the relative efficiency of the considered memory technologies.

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Exploring MRAM Technologies for Energy Efficient Systems-On-Chip

Cited by 28 publications

References 51 publications

Magnetic Tunnel Junction Applications

Magnetic Tunnel Junction Applications

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs

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