Exploring new features of high-bandwidth memory for GPUs

Li, Bingchao; Song, Choungki; Jiang, Wei; Ahn, Jung Ho; Kim, Nam Sung

doi:10.1587/elex.13.20160527

Cited by 6 publications

(7 citation statements)

References 14 publications

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“…GEM-5 does not have an energy model for HBM. So we created a model based on DDR4 as described in [37]. The energy consumption of through-silicon vias (TSV) was not considered.…”

Section: B Energy Resultsmentioning

confidence: 99%

“…For the energy models, we employ the models integrated in GEM-5, where the energy model of HBM is not supported. Hence, we properly built the HBM energy models based on [37]. We simulated the performance and the energy of seven architectures: 1) DRAM normally refreshed, VOLUME 4, 2016 This work is licensed under a Creative Commons Attribution 4.0 License.…”

Section: Discussionmentioning

confidence: 99%

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ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

Nguyen

et al. 2021

IEEE Access

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In sub-20nm technologies, DRAM cells suffer from poor retention time. With the technology scaling, this problem tends to be worse, significantly increasing refresh power of DRAM. This is more problematic in memory heavy applications such as deep learning systems, where a large amount of DRAM is required, DRAM refresh power contributes to a considerable portion of total system power. With the growth in deep learning workloads, this is set to get worse. In this work, we present a zero-cycle bit-masking (ZEM) scheme that exploits the asymmetry of retention failures, to eliminate DRAM refresh in the inference of convolution neural networks, natural language processing, and the image generation based on generative adversarial network. Through careful analysis, we derive a bit-error-rate (BER) threshold that does not affect the accuracy of inference. Our proposed architecture, along with the techniques involved, are applicable to all types of DRAMs. Our results on 16Gb devices show that ZEM can improve the performance by up to 17.31% while reducing the total energy consumed by DRAM by up to 43.03%, dependent on the type of DRAM.

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“…GEM-5 does not have an energy model for HBM. So we created a model based on DDR4 as described in [37]. The energy consumption of through-silicon vias (TSV) was not considered.…”

Section: B Energy Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

Nguyen

et al. 2021

IEEE Access

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“…Some initial works present HBM as an emerging memory standard that can provide bandwidth superior to 256GB/s as well as offers lower power consumption [22]. More recent works compare HBM and DDR for high performance systems [4]. [18] presents the challenges of capacity scaling of HBM device by stacking more DRAM dies to make a taller stack.…”

Section: Synthetic Experimentsmentioning

confidence: 99%

“…Also, unlike the other variant of 3Dstacked DRAM -Hybrid Memory Cube (HMC), HBM is adopted as a JEDEC standard, implements much wider data bus and resides on the same silicon interposer as the processing unit. HBM, common in GPUs, FPGA-CPUs and System on Chips like the Xilinx UltraScale+, is better equipped to handle increased memory requirements of GPU and accelerator-based architectures [4], [5]. A recent study suggests the combination of low power consumption and high bandwidth make this category of memory ideal for embedded systems as well [6].…”

Section: Introductionmentioning

confidence: 99%

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

Asifuzzaman

Abuelala

Hassan

et al. 2021

2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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The number of functionalities controlled by software on every critical real-time product is on the rise in domains like automotive, avionics and space. To implement these advanced functionalities, software applications increasingly adopt artificial intelligence algorithms that manage massive amounts of data transmitted from various sensors. This translates into unprecedented memory performance requirements in critical systems that the commonly used DRAM memories struggle to provide. High-Bandwidth Memory (HBM) can satisfy these requirements offering high bandwidth, low power and high-integration capacity features. However, it remains unclear whether the predictability and isolation properties of HBM are compatible with the requirements of critical embedded systems. In this work, we perform to our knowledge the first timing analysis of HBM. We show the unique structural and timing characteristics of HBM with respect to DRAM memories and how they can be exploited for better time predictability, with emphasis on increased isolation among tasks and reduced worst-case memory latency.

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“…The diversity of high-speed I/O standards for DRAM requires an automated way of doing production tests over a variety of channels [1,2,3,4,5,6,7]. DRAM standards, such as DDR4, LPDDR4, GDDR5, and HBM address different application-specific needs in PCs, mobile devices, graphics processors, and artificial intelligence (AI) accelerators, respectively [8,9,10,11], and use different I/O channels whose loss characteristics span a wide variety, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Kim

2019

IEICE Electron. Express

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This paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed dynamic random-access memory (DRAM) channels, with an aim to facilitate an automated test procedure for a DRAM interface, which does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that has experienced adjustable amounts of skin-effect loss and dielectric loss in electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and lowbandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip, fabricated in a 65-nm CMOS process, occupies an area of 5200 µm 2 and operates over 1.4-7 Gbps while dissipating 38 mW at 7 Gbps. It is demonstrated that the implemented transmitter can emulate 10-40"-long microstrip lines on an FR4 grade material with a peak error less than 12.5% in the pulse response.

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Exploring new features of high-bandwidth memory for GPUs

Cited by 6 publications

References 14 publications

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

ZEM: Zero-Cycle Bit-Masking Module for Deep Learning Refresh-Less DRAM

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

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