Exploring Optimal Topology and Routing Algorithm for 3D Network on Chip

Abstract

<b>Problem statement:</b> Network on Chip (NoC) is an appropriate candidate to implement interconnections in SoCs. Increase in number of IP blocks in 2D NoC will lead to increase in chip area, global interconnect, length of the communication channel, number of hops transversed by a packet, latency and difficulty in clock distribution. 3D NoC is evolved to overcome the drawbacks of 2D NoC. Topology, switching mechanism and routing algorithm are major area of 3D NoC research. In this study, three topologies (3D-MT, 3D-ST and 3D-RNT) and routing algorithm for 3D NoC are presented. <b>Approach:</b> Experiment is conducted to evaluate the performance of the topologies and routing algorithm. Evaluation parameters are latency, probability and network diameter and energy dissipation. <b>Results:</b> It is demonstrated by a comparison of experimental results analysis that 3D-RNT is a suitable candidate for 3D NoC topology. <b>Conclusion:</b> TThe performance of the topologies and&#13; routing algorithm for 3D NoC is analysed. 3D-MT is not a suitable candidate for 3D NoC, 3D-ST is a&#13; suitable candidate provided interlayer communications are frequent and 3D-RNT is a suitable&#13; candidate as interlayer communications are limited

Volumetric Degenerative Routing for 3D Network-on-chip

“…Other conventional approaches include performing routing along the Z-axis to the required layer and then performing West-First, North-Last, NegativeFirst, Odd-Even algorithm. Viswanathan et al put forward a new architecture for 3D NOC and a hierarchical routing scheme to transfer flits [11]. The architecture is that each node in a layer is a Cluster Head (CH) and is connected to four PEs.…”