Exploring parallelism in short sequence mapping using Burrows-Wheeler Transform

Bozdağ, Doruk; Hatem, Ayat; Çatalyürek, Ümit V.

doi:10.1109/ipdpsw.2010.5470897

Cited by 5 publications

(2 citation statements)

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“…Each node then produces an alignment output file in SAM format, and the files from all nodes are merged into a single file at the end of the job. Our approach is different from [23], which did not use MPI, but looked at different partitioning of reads and genomes over nodes. Our partitioning of the Inchworm contigs over nodes is a special case of their more general study.…”

Section: A Mpi Implementation Of Bowtiementioning

confidence: 99%

Parallelization of the Trinity Pipeline for De Novo Transcriptome Assembly

Sachdeva

Kim

Jordan

et al. 2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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This paper details a distributed-memory implementation of Chrysalis, part of the popular Trinity workflow used for de novo transcriptome assembly. We have implemented changes to Chrysalis, which was previously multi-threaded for sharedmemory architectures, to change it to a hybrid implementation which uses both MPI and OpenMP. With the new hybrid implementation, we report speedups of about a factor of twenty for both GraphFromFasta and ReadsToTranscripts on an iDataPlex cluster for a sugarbeet dataset containing around 130 million reads. Along with the hybrid implementation, we also use PyFasta to speed up Bowtie execution by a factor of three which is also part of the Trinity workflow. Overall, we reduce the runtime of the Chrysalis step of the Trinity workflow from over 50 hours to less than 5 hours for the sugarbeet dataset. By enabling the use of multi-node clusters, this implementation is a significant step towards making de novo transcriptome assembly feasible for ever bigger transcriptome datasets.

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Section: A Mpi Implementation Of Bowtiementioning

confidence: 99%

Parallelization of the Trinity Pipeline for De Novo Transcriptome Assembly

Sachdeva

Kim

Jordan

et al. 2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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“…In [21], six parallelization methods are proposed, including partitioning the reads, the genome, and both the reads and the genome. The parallelization strategies investigated in [24] try to optimize data distribution for parallel execution of BWT-based algorithms. In contrast, we focus on single-thread optimization in this paper, which is orthogonal to those workload partitioning strategies, in this regard their work can be used to extend our work.…”

Section: Related Workmentioning

confidence: 99%

Investigating Memory Optimization of Hash-index for Next Generation Sequencing on Multi-core Architecture

Wang¹,

Tang²,

Li³

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Abstract-Next Generation Sequencing (NGS) is gaining interests due to the increased requirements and the decreased sequencing cost. The important and prerequisite step of most NGS applications is the mapping of short sequences, called reads, to the template reference sequences. Both the explosion of NGS data with over billions of reads generated each day and the dataintensive computations pose great challenges to the capability of existing computing systems. In this paper, we take a hashindex based algorithm (PerM) as an example to investigate the optimization approaches for accelerating NGS reads mapping on multi-core architectures. First, we propose a new parallel algorithm that reorders bucket access in hash index among multiple threads so that data locality in shared cache is improved. Second, in order to reduce the number of empty hash bucket, we propose a serialized hash index compression algorithm, which coincides with the sequential access nature of our new parallel algorithm. With reduced hash index size, it also becomes possible for us to use longer hash keys, which alleviates the hash conflicts and improves the query performance. Our experiment on an 8-socket 8-cores Intel Xeon X7550 SMP with 128 GB memory shows that the new parallel algorithm reduces LLC miss ratio to be 8% ∼ 15% of the original algorithm and the overall performance is improved by 4 ∼ 11 times (6 times avg.).

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