Exploring parallelization techniques based on OpenMP in H.264/AVC encoder for embedded multi-core processor

Jo, Seongmin; Jo, Song Hyun; Song, Yong Ho

doi:10.1016/j.sysarc.2012.06.005

Cited by 6 publications

(9 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Firstly, GOPs are a coding-independent unit. Therefore, the GOP level is easy to implement; however, it has long latency [25] and large memory requirements [5]. Thus, paralleling the GOP level is inappropriate for shared memory architecture because of limited on-chip memory [25].…”

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

“…Moreover, this level of coding is associated with large memory requirements. Thirdly, slicelevel coding has been associated with minimal synchronization cost, normal memory requirements, and good performance scalability [5]. The only drawbacks associated with this level are the increasing bit rate and degradation of visual quality when the number of slices increases [13].…”

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

“…The only drawbacks associated with this level are the increasing bit rate and degradation of visual quality when the number of slices increases [13]. Fourthly, MB-level and block-level coding incur no bit rate degradation; nevertheless, both are associated with high synchronization costs because of the small-sized parallel unit, dependency among them [17], and poor scalability [5], which render them incompatible with the current trend of multicore. Given this remarks, parallel granularity in video coding could potentially reflect the performance of a parallel system in terms of scalability, synchronization cost, and memory requirements.…”

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

“…In a view of the H.264 codec, it has been proved that the data-level parallelization has outperformed the task-level parallelization [5] due to the several kinds of dependencies among the coding components of the H.264 codec. This paper presents reviews some of the attempts aimed at lessening the complexity of the H.264 vide coding standard based on datalevel parallelism utilizing different parallel architectures.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Aboalmaaly¹

2017

ijecs

View full text Add to dashboard Cite

Abstract:In order to enable easier transmission and storage of videos, video-coding techniques are used as data compression process that is intended to reduce the size of raw video without sacrificing its visual quality. The H.264 is relatively one of the recent video compression standards, which has proved to outperform former standards in terms of compression efficiency. However, it's associated with mush higher computational complexity. Several software-based as well as hardware-based approaches have been suggested to tackle this problem by using several flavours of data-level parallel approaches for the encoder and decoder sides. In this paper, these approaches are presented and compared in form of a comparative review. The suitability of one particular approach is determined based to the architecture used.

show abstract

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

Section: Comparison Of the H264 Data-level Parallelismsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Aboalmaaly¹

2017

ijecs

View full text Add to dashboard Cite

show abstract

“…Multi-processor, multicore, multithreading encoding system and parallel algorithms have been discussed in many papers [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. This paper presents the frame level parallelism (FLP) approach and describes its complete implementation for H.264/AVC encoder using a multicore DSP TMS320C6472.…”

Section: Introductionmentioning

confidence: 99%

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Bahri

Belhadj²,

Grandpierre³

et al. 2014

J Real-Time Image Proc

View full text Add to dashboard Cite

International audienceThe latest generation of multicore digital signal processors (DSP), their high computing power, low consumption, and integrated peripherals will allow them to be embedded in the next generation of smart camera. Such DSPs allow designers to evolve the vision landscape and simplify the developer’s tasks to run more complex image and video processing applications without the need to burden a separate personal computer. This paper explains the exploitation of the computing power of a multicore DSP TMS320C6472 to implement a real-time H264/AVC video encoder. This work can be considered as a milestone for the implementation of the new High Efficiency Video Coding standard (HEVC-H265). In fact, to improve the encoding speed, enhanced Frame Level Parallelism (FLP) approach is presented and implemented. A real-time fully functional video demo is given, taken into account video capture and bitstream storage. Experimental results show how we efficiently exploit the potentials and the features of the multicore platform without inducing video quality degradation in terms of PSNR or bitrate increase. The enhanced FLP using five DSP cores achieves a speedup factor of more than four times in average compared to a mono-core implementation for Common Intermediate Format (CIF 352 × 288), Standard Definition (SD 720 × 480), and High Definition (HD 1280 × 720) resolutions. This optimized implementation allows us to meet the real-time compliant by reaching an encoding speed of 99 f/s (frame/second) and 30 f/s for CIF and SD resolutions respectively, and saves up to 77 % of encoding time for HD resolution

show abstract

Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP

Bahri

Grandpierre

Ayed

et al. 2016

J Sign Process Syst

View full text Add to dashboard Cite

To overcome high computational complexity of advanced video encoders for emerging applications that require real-time processing, using multicore technology can be one of the promising solutions to meet this constraint. In this context, this paper presents a parallel implementation of the H264/AVC high definition (HD) video encoder exploiting the power processing of eight-core digital signal processor (DSP) TMS320C6678. GOP Level Parallelism approach is used to improve the encoding speed and meet the real-time encoding compliant. A master core is reserved to handle data transfer between the DSP and the camera interface via a Gigabit Ethernet link. Multithreading algorithm and ping-pong buffers technique are used to enhance the classic GOP level parallelism approach and hide communication overhead. Experimental results on seven slave DSP cores, running each at 1 GHz, show that our implementation allows performing a real-time HD (1280x720) video encoding. The achieved encoding speed is up to 28 f/s. The proposed parallel implementation accelerates the encoding process by a factor of 6.7 without inducing quality degradation in terms of PSNR or bit-rate increase compared to single core implementation. Experiments show that our proposed scheduling technique for hiding communication overhead allows saving up to 36% of the fully encoding chain time which includes frames capturing, frames encoding and bitstream saving in a file.

show abstract

Exploring parallelization techniques based on OpenMP in H.264/AVC encoder for embedded multi-core processor

Cited by 6 publications

References 17 publications

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Data-Level Parallel Approaches for the H.264/AVC: A Review from the Encoder and the Decoder Perspectives

Real-time H264/AVC encoder based on enhanced frame level parallelism for smart multicore DSP camera

Embedded Real-Time H264/AVC High Definition Video Encoder on TI’s KeyStone Multicore DSP

Contact Info

Product

Resources

About