Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Ness, Drew C.; Hescott, C.J.; Lilja, David J.

doi:10.1145/1228784.1228838

Cited by 3 publications

(4 citation statements)

References 25 publications

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“…The second stage consists of applying the threshold to create a suitable subset of robust cells. The usual tuning of a library creates a subset of cells by excluding complete cells [4,5,6]. In this approach, instead of removing a cell completely, a restriction on the look-up table is imposed.…”

Section: B Convolution Of Probability Distributionsmentioning

confidence: 99%

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Standard cell library tuning for variability tolerant designs

Fabrie¹,

Echeverri²,

Vertreg³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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DisclaimerThis document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-In today's semiconductor industry we see a move towards smaller technology feature sizes. These smaller feature sizes pose a problem in terms of process controllability, e.g. mismatch between identical cells on a single die known as local variation. In this paper a library tuning method is proposed which makes a smart selection of cells in a standard cell library to reduce the design's sensitivity to local variability. This results in a robust IC design with an identifiable behavior towards local variations. Experimental results performed on a widely used microprocessor design synthesized for a high performance timing show that we can achieve a timing spread reduction of 37% at an area increase cost of 7%.

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Section: B Convolution Of Probability Distributionsmentioning

confidence: 99%

“…There are examples for which library tuning is used to reduce soft errors [4], here different subsets are generated and used in synthesis to analyze their behavior to soft errors. Library tuning as used in [5] is meant to iteratively remove cells from the library to pursue a synthesis speed-up.…”

Section: Introductionmentioning

confidence: 99%

Standard cell library tuning for variability tolerant designs

Fabrie¹,

Echeverri²,

Vertreg³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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“…One of them is selected to apply the developed methodology and then obtain a new characterization. In this case, the selected library's name is SXLIB [3].…”

Section: Standard Cell Librarymentioning

confidence: 99%

Characterization technique to implement self-timed cells for VLSI design blocks

Cisneros

Panduro

Baron

et al. 2014

2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)

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In this article, a methodology to obtain the characterization of the standard cell library called SXLIB is presented, this library is available within Alliance tools. The later proposal is developed based on the spreading analysis that the signal has throughout each cell, this with the objective of obtaining a delay time according to the technology of the manufacture's receiver. This characterization technique can be used with any set of standard cells, for a manufacturing technology that differs by the default one used by Alliance, then, the results of the new characterization are presented of the specified library SXLIB. The importance of knowing the spreading time of the signal, is due to the required time to include the necessary delays in the design of self-timed structures. This is, one of the key phases of the design and synthesis process, expressed in structural language VHDL that generates Alliance tools. Throughout this phase, the designer will prove that the IC works under the desired behavior, in form (logic operation) as in time (maximum and minimum delays, maximum work frequencies, etc.). That is because the obtained results from using the characterized library represent a key point in the design of self-timed structures.

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“…In relation to the probability of a soft error being generated, cell supply voltage, sizing parameters, and transient waveform descriptions have been used to predict the resulting upset rate (Ness et al, 2007;Zhang and Wang, 2006). In relation to the probability that an error propagates, Krishnaswamy et al showed that the likelihood of an error propagating is directly related to signal observability and probability (Krishnaswamy et al, 2007).…”

Section: Reliabilitymentioning

confidence: 99%

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

Limbrick

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Cited by 3 publications

References 25 publications

Standard cell library tuning for variability tolerant designs

Standard cell library tuning for variability tolerant designs

Characterization technique to implement self-timed cells for VLSI design blocks

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits

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