Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform

Silva, Lucas B. da; Almeida, Danilo; Nacif, José Augusto M.; Sánchez-Osorio, Ismael; Hernández-Martínez, Carlos Alberto; Ferreira, Ricardo

doi:10.1109/reconfig.2017.8279791

Cited by 12 publications

(27 citation statements)

References 26 publications

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“…In addition for the GRN, the Theoretical Bound and the GOPs are not depicted in Table since the operations are fine grained (Bit Boolean operations), and the network state computation has a variable length execution time. On average, as shown in the work of da Silva et al, a state computation spends around 80 simulation steps. Each step evaluates the set of the Boolean equations three times, where each set has 272 Boolean operations.…”

Section: Resultsmentioning

confidence: 94%

“…One way is to focus on application and domain‐specific accelerators: Neural network, Bayesian learning, bioinformatics, stencil computing, energy‐efficient accelerators for graph analytics algorithms, and irregular applications mapping . Another way is to focus on Domain‐Specific Language (DSL) which aims representing parallelism in stream‐based applications, like SPar based on C++ …”

Section: Related Workmentioning

confidence: 99%

“…Therefore, the FPGA peak performance could achieve

25600 \frac{M e x p r e s s i o n s}{s e c}

, which represents a theoretical speed‐up of about 30. Furthermore, the real scenario is even more favorable to the FPGA approaches, for instance, the CAC GRN computation is 174.2 times faster than a 20‐core multiprocessor in the work of da Silva et al…”

Section: Performance Metrics and Analysismentioning

confidence: 99%

“…The second feature is the introduction of asynchronous operators. The GRN algorithm presented in the aforementioned work computes the transient size and the steady cycle for each network state. These computations could be performed in parallel by using more than one accelerator unit.…”

Section: Performance Metrics and Analysismentioning

confidence: 99%

“…The accelerator GRN generator presented in the work of da Silva et al has a memory interface customized to get the maximum performance for the first Intel CPU‐FPGA platform, which was discontinued. Therefore, we create an accelerator unit by reusing the GRN kernel from the aforementioned work as shown a simplified diagram in Figure C. For the CPU interface, we use the ADD portable interface memory manager.…”

Section: Performance Metrics and Analysismentioning

confidence: 99%

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ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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Section: Resultsmentioning

confidence: 94%

Section: Related Workmentioning

confidence: 99%

“…Therefore, the FPGA peak performance could achieve

25600 \frac{M e x p r e s s i o n s}{s e c}

Section: Performance Metrics and Analysismentioning

confidence: 99%

Section: Performance Metrics and Analysismentioning

confidence: 99%

Section: Performance Metrics and Analysismentioning

confidence: 99%

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ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Gene regulatory accelerators on cloud FPGA

Penha

Bragança

Canesche

et al. 2023

Concurrency and Computation

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SummaryGene regulatory networks (GRN) are dynamic models in time and space. These models are used to predict diseases and in drugs research. GRN models are discrete, and Boolean graphs can efficiently represent them. However, GRN algorithms explore a large solution space with high computational complexity. This work proposes efficient FPGA‐based accelerators to implement two GRN algorithms: attractor computation and Derrida plot. Nevertheless, FPGA accelerator design and deployment are still a challenge. This work presents an accelerator design framework for AWS Amazon FPGA cloud. The framework simplifies the software (SW) and hardware (HW) generation for GRN accelerators. The user provides a high‐level model for the Boolean GRN, and our tool automatically creates AWS‐ready‐to‐deploy software and hardware components. For the attractor and the Derrida plot computation, the proposed FPGA accelerators are on average and faster than a V100 GPU.

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RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

Vieira

Canesche

Bragança

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Coarse-grained reconfigurable architectures (CGRA) are a power-efficient approach for hardware accelerators. However, there are few EDA tools for CGRA. We develop hardware-based placement and routing (P&R) for fully-pipelined CGRA mapped as an FPGA overlay. The key idea is to use the available FPGA resources to replicate several mapping units, thus exploring parallel execution, area/execution time trade-offs, and achieving near-optimal mapping solutions. Furthermore, our P&R provides portability and an incremental run-time approach. In comparison to VPR and CGRA-ME tools and a time-multiplexer approach, our spatial mapping reduces the P&R execution time, and it improves the performance up to hundreds of Gops/s by using fully-pipelined architectures.

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Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform

Cited by 12 publications

References 26 publications

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Gene regulatory accelerators on cloud FPGA

RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays

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