Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Sreenivasulu, V. Bharath; Neelam, Aruna Kumari; Kola, Sekhar Reddy; Singh, Jawar; Li, Yiming

doi:10.1109/access.2023.3306050

Cited by 19 publications

(7 citation statements)

References 30 publications

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“…The DIBL and SS are crucial short-channel parameters that determine the performance of devices. In these devices, drain potential has a significant influence on the energy band diagram in the channel region [18]. The drain bias unintentionally lowers the barrier between the source and drain, resulting in a subthreshold current, and the effect is commonly referred to as DIBL.…”

Section: Resultsmentioning

confidence: 99%

“…Insulators are used in the spacing area to reduce parasitic capacitance, which increases resistance. To achieve this, single and dual dielectric spacer materials are used to fill the region created between the gate and source/drain [16][17][18]. These regions contribute to reducing SCE and improving device performance.…”

Section: Device Structures and Simulation Methodsmentioning

confidence: 99%

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Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Panigrahy,

Amudalapalli,

Rani

et al. 2024

IEEE Access

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This work investigates the effect of single and dual-k spacer materials consisting of different dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) employing hafnium oxide and silicon dioxide as gate insulator to improve its sub-threshold performance. The effect of the external lowk spacer modification in the dual-k spacer has been shown by adjusting the inner high-k spacer. The draininduced barrier lowering (DIBL) in this modification with dual-k spacer is 14 mV/V, which is a significant improvement above single spacer NS-FET. The Visual TCAD 3D Cogenda tool is used to examine the performance of the developed NS-FET with air, single, dual-k, and hybrid spacers. The CADENCE platform is used to perform circuit aspects. Additionally, a comparison of the device architecture's performance study with respect to DC characteristics is made. DC parameters of the proposed device are established: ION to IOFF ratio of approximately 10 5 , DIBL of approximately 14 mV/V, sub-threshold swing (SS) of approximately 62 mV/dec, and low threshold voltage (Vth) of 0.38 V. The analysis on power consumption for advanced NS-FET is also analyzed with single-k and dual-k spacers. The performance of single-k and dual-k spacer dielectric variation for CMOS inverter is also shown. Furthermore, low power consumption by this NS-FET ensures improved device performance suitable for nanoscale semiconductor industries.

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Section: Resultsmentioning

confidence: 99%

Section: Device Structures and Simulation Methodsmentioning

confidence: 99%

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Panigrahy,

Amudalapalli,

Rani

et al. 2024

IEEE Access

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“…Incessant scaling of SNS-FETs beyond the sub-7 nm node increases the leakage current and subthreshold slope (SS) [9]. The literature reports that the SS of N-SNS-FET and P-SNS-FET is 83 mV/decade and 94 mV/ decade, respectively [10].…”

Section: Introductionmentioning

confidence: 99%

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

Jain,

Sawhney,

Kumar

2024

Phys. Scr.

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The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by A and improves the switching ratio by . An increase in the source doping level from to cm-3 results in a decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is cm-3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

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“…As technology advances beyond the 5 nm nodes, stacked nanosheet (NS) gate-all-around (GAA) FETs are anticipated to take over from FinFETs [3], [4]. This shift is due to their superior gate control, elevated current density per device footprint, and the ability to adjust sheet width, which facilitates adaptable circuit design [5], [6]. Having a flexible and expanded channel width provides the confidence to achieve a substantial ON current through the vertical arrangement of slender conducting channels.…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective

Kumari,

Sreenivasulu,

Vijayvargiya

et al. 2024

IEEE Access

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In this article, the comparison of nanosheet (NS) FET, CombFET, and TreeFETs at advanced technology nodes is performed. Initially, the DC metrics like ION, ION/IOFF and ID-VDS are dominated by TreeFET compared to Comb and NSFET. The TreeFET exhibits higher ION and ensures high-performance (HP) applications at advanced nodes. However, the NSFET continues as a better performer towards low power (LP) applications. The TreeFET dominates the performance and switching performance for temperature variation. At lower temperatures, the NS, Comb, and TreeFETs have a marginal impact on IOFF. The analog performance is dominated by TreeFET due to higher ION. The NSFET exhibits lower Cgd and Cgs due to the absence of interbridges (IB) between channels. The RF performance is also dominated by Comb and TreeFETs due to the presence of IBs. Further, TreeFET based CMOS inverter outperforms in terms of switching current (ISC) compared to the NSFET and CombFET counterparts. The 27-stage ring oscillator (RO) performance of TreeFET dominates Comb and NSFET with 11.56 GHz ensuring driving radio frequency applications. Thus, the paper will give deep insights into the performance of emerging FETs at both device as well as circuit levels.

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Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Cited by 19 publications

References 30 publications

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective

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