Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors

Matthews, Eric; Gao, Yuhui; Shannon, Lesley

doi:10.1109/fccm48280.2020.00025

2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) 2020

DOI: 10.1109/fccm48280.2020.00025

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Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors

Eric Matthews

Yuhui Gao

Lesley Shannon

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2024

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Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors

Keilbart,

Gao,

Chua

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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Field Programmable Gate Arrays (FPGAs) are commonly used to accelerate floating-point (FP) applications. Although researchers have extensively studied FPGA FP implementations, existing work has largely focused on standalone operators and frequency-optimized designs. These works are not suitable for FPGA soft processors which are more sensitive to latency, impose a lower frequency ceiling, and require IEEE FP standard compliance. We present an open-source floating-point unit (FPU) for FPGA RISC-V soft processors that is fully IEEE compliant with configurable levels of FP precision. Our design emphasizes runtime performance with 25% lower latency in the most common instructions compared to previous works while maintaining efficient resource utilization. Our FPU also allows users to explore various mantissa widths without having to rewrite or recompile their algorithms. We use this to investigate the scalability of our reduced-precision FPU across numerous microbenchmark functions as well as more complex case studies. Our experiments show that applications like the discrete cosine transformation and the Black-Scholes model can realize a speedup of more than 1.35x in conjunction with a 43% and 35% reduction in lookup table and flip-flop resources while experiencing less than a 0.025% average loss in numerical accuracy with a 16-bit mantissa width.

show abstract

Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors

Keilbart,

Gao,

Chua

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

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Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-Processors

Cited by 1 publication

References 17 publications

Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors

Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors

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