EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability

Halambi, Ashok; Grun, Peter; Khare, Asheesh; Dutt, Nikil; Nicolau, Alex

doi:10.1007/978-1-4020-6488-3_3

Cited by 10 publications

(2 citation statements)

References 7 publications

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“…Such pre-processing is cumbersome, error-prone and distorts optimization efforts. Likewise, solutions that are automated but produce decoders that linearly traverse instructions are also considered inapplicable for instruction sets in the range of several hundred [1,[14][15][16]. We will therefore concentrate on the five published solutions which output…”

Section: Functional Analysis Of Decoder Decision Tree Algorithmsmentioning

confidence: 99%

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Tadros

2023

ECMS 2023 Proceedings Edited by Enrico Vicario, Romeo Bandinelli, Virginia Fani, Michele Mastroianni

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Instruction decoders are indispensable components of instruction set simulators and processor toolchains. The lengthy and elaborate manual implementation of decoders can be greatly alleviated by decoder generation tools. These need to handle the rising complexity of modern instruction sets, notably irregularities such as non-uniform opcodes and logic propositions on bit fields. In addition, decoder generators need to provide cost-optimized solutions, as the efficiency of the decoding module can have a substantial effect on the overall performance. This paper analyzes five published algorithms for decoder generators from two perspectives: First, in terms of functionality, we systematically assess how each tool handles different properties of modern instruction sets, highlighting properties that are challenging, unhandled by current algorithms or even result in functionally erroneous decoders. Second, we challenge seemingly intuitive definitions of decoder optimality using a sophisticated model of decision tree cost. We validate this analytical model against an experimental performance evaluation of generated decoders for SPARC, MIPS32 and ARMv7 platforms. For our analysis, we implemented all five algorithms after correcting the discovered conceptual errors and extending them to handle the above-mentioned ISAs. Our work reveals that state-of-the-art decoder generation tools are unable to fully and correctly handle complex ISAs and adopt an erroneous notion of optimality.

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Section: Functional Analysis Of Decoder Decision Tree Algorithmsmentioning

confidence: 99%

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Tadros

2023

ECMS 2023 Proceedings Edited by Enrico Vicario, Romeo Bandinelli, Virginia Fani, Michele Mastroianni

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“…A ADL EXPRESSION [39] é voltada para a modelagem de arquiteturas System-on-Chip (SoC). A linguagem segue uma abordagem mista, capturando a especificação estrutural e comportamental de forma natural de arquiteturas programáveis, consistindo de processadores, coprocessadores e memórias.…”

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Desafios no desenvolvimento de plataformas capazes de executar sistemas operacionais utilizando o ArchC

Cardoso¹

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Design challenges in electronic systems increase with their size and the design requirements, leading to even more pressure in time-to-market issues. Traditional approaches like RTL become unaffordable, due to the need for parallel development of hardware and software necessity. In this context, modern methodologies like ESL have been successfully used to tackle this kind of problem. With the increasing number of features and the complexity of the applications to that new devices, these devices, in major, may need an embedded operating system. This poses a challenge in the homogeneous development of hardware and software, demanding a complex virtual platform development, capable of running an operating system and its applications. But, developing this kind of platform is not a simple task.This work presents an ArchC System Level Platform implementation, based on LEON architecture. This platform can execute a Linux operating system and user applications with virtual memory support. It besides demonstrates the challenges and limitations of the ArchC tools on development of this type of platform. ix x ResumoCom o aumento da complexidade dos sistemas eletrônicos, novos desafios foram surgindo na fase de projeto desses sistemas; assim, os requisitos de projeto estão cada vez mais complexos, implicando diretamente no time-to-market que torna-se cada vez mais difícil de ser cumprido. As abordagens tradicionais como o projeto RTL tornaram-se impraticáveis visto que é cada vez mais evidente a necessidade da criação de software paralelamente ao projeto de hardware. Nesse contexto, metodologias modernas como ESL têm sido utilizadas com sucesso, para que os projetistas possam solucionar esses problemas. Com o crescente número de funcionalidades que os novos dispositivos implementam e o aumento da complexidade das aplicações, muitas vezes exigem que esses dispositivos rodem um sistema operacional embarcado. Isso dificulta ainda mais o desenvolvimento homogêneo hardware/software, pois demanda a criação de plataformas virtuais completas capazes de executarem um sistema operacional e suas aplicações, e o desenvolvimento dessas plataformas não é uma tarefa trivial.Este trabalho apresenta a implementação de uma plataforma, em nível de sistema, completa da arquitetura LEON, utilizando a ferramenta ArchC. A plataforma apresentada permite executar um sistema operacional Linux e suas aplicações, com suporte a gerenciamento de memória virtual. Além de demonstrar as dificuldades e as limitações da ferramenta ArchC na geração desse tipo plataformas. xi xiiDedico esse trabalho em memória do meu irmão Raphael que eu gostaria que ainda estivesse aqui para compartilhar desse momento. xiii xiv AgradecimentosEu gostaria de agradecer aos professores Rodolfo Jardim Azevedo e Sandro Rigo pela orientação no Mestrado ao longo desses anos. Obrigado pela dedicação, ideias e conselhos que foram fundamentais para o desenvolvimento desse trabalho. Especialmente ao professor Rodolfo pelo grande apoio pessoal com as dificuldades e os revezes nesses último...

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Application-Specific Processors

Mitra¹

2017

Handbook of Hardware/Software Codesign

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EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability

Cited by 10 publications

References 7 publications

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Functional Analysis And Performance Evaluation Of Decoder Decision Tree Generation Algorithms

Desafios no desenvolvimento de plataformas capazes de executar sistemas operacionais utilizando o ArchC

Application-Specific Processors

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