Using a reduced pressure-chemical vapor deposition cluster tool, we have studied the epitaxial growth of Si using either a silane or a dichlorosilane+hydrochloric acid chemistry on fullsheet, patterned and silicon-on-insulator (SOI) substrates. We have first of all developed a (''HF-last'' advanced wet cleaning+low thermal budget (775 C, 2 min) in situ H 2 bake) combination that yields atomically smooth, contamination free Si starting surfaces for both fullsheet and patterned wafers. We have then modeled the low temperature Si growth rate (silane or dichlorosilane+hydrochloric acid chemistry) on fullsheet wafers. A similar growth rate activation energy is found for both chemistries, i.e. E GR B50 kcal mol À1. The growth rate dependency on the Si precursor flow is vastly different, however. Fitting this dependency with a simple power law, a value of 0.36 is indeed associated to dichlorosilane, versus 0.92 for silane. The HCl etching rate is characterized by an activation energy E ER B34 kcal mol À1 , with a 0.52 power law dependency on the HCl flow. On patterned wafers, we have demonstrated that a deposited Si thickness limit (20 nm) exists at 775 C for high F ðHClÞ=F ðSiH 2 Cl 2 Þ mass flow ratios. This limit disappears when (i) F ðHClÞ=F ðSiH 2 Cl 2 Þ is reduced (ii) the growth temperature is increased to 800 C. Finally, we have highlighted the specifics of the growth on SOI wafers. A significant growth rate reduction (compared to bulk Si) has been evidenced on ultra-thin Si over-layer SOI wafers. It gets less and less pronounced as the buried oxide layer gets thinner and/or the Si over-layer thickness increases.