Expression-tree-based algorithms for code compression on embedded RISC architectures

Abstract

Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven efforts aimed at designing processors with shorter instruction formats (e.g., ARM Thumb and MIPS16) or able to execute compressed code (e.g., IBM PowerPC 405). This paper proposes three code compression algorithms for embedded RISC architectures. In all algorithms, the encoded symbols are extracted from program expression trees. The algorithms differ on the granularity of the encoded symbol, which are selected from whole trees, parts of trees, or single instructions. Dictionary-based decompression engines are proposed for each compression algorithm. Experimental results, based on SPEC CINT95 programs running on the MIPS R4000 processor, reveal an average compression ratio of 53.6% (31.5%) if the area of the decompression engine is (not) considered.Index Terms-Code compression, RISC architecture.

Clustering-Based Microcode Compression

“…Araujo et al [1] presented three methods for code compression: Pattern Based, Tree Based and Instruction Based Compression, achieving a compression ratio of 61.3%, 60.7% and 53.6% respectively. Again, the complexity of decoding hardware hinders application of this technique to microcode.…”

“…The number of alternative encodings of the operations and fields grows combinatorially. This makes techniques like Instruction-Based Compression [1] less likely to succeed. Second, microcode is usually handcoded and crafted for performance.…”

“…So, the decompression engine must have low latency and enable high throughput instruction flow. For such reasons, it is desirable to avoid variable-length encoding compression techniques [1], [14], [19], [20], as these approaches require a more complex decoder, incurring costs in area and power, in addition to longer design and verification times.…”

Multi-profile based code compression

“…Lefurgy et al [9] experiments used fixed and variable-length codewords 1 . In their first method, 16-bit fixed-length codewords are used with a 256-entry dictionary, each entry containing up to 4 instructions in sequence.…”

“…Since the Compressed Code RISC Processor -CCRP [15] was introduced, many compression techniques have been shown to be efficient in code compression [1,3,11] and a few have been adopted by industry [7,12]. Recently, researchers have realized that the benefits of compression go beyond reducing code size, reaching performance improvement and energy consumption reduction [2,10].…”