Extended Fault Detection Techniques for Systems-on-Chip

Abstract

The adoption of Systems-on-Chip (SoCs) in different types of applications represents an attracting solution. However, the high integration level of SoCs increases the sensitivity to transient faults and consequently introduces some reliability concerns. Several solutions have been proposed to attack this issue, mainly intended to face faults in the processor or in the memory.In this paper, we propose a solution to detect transient faults affecting data transmitted between the microprocessor and the communication peripherals embedded in a SoC. This solution combines some modifications of the source code at high level with the introduction of an Infrastructure IP (I-IP) to increase the dependability of the SoC.

Power-Aware Reliable Embedded Software Design

“…The remaining blocks whose execution frequency did not reach this minimum execution frequency level did not receive the embedded signatures. In summary, if we consider a threshold of 0%, all nodes of the control-flow graph receive check-points (let us define this condition as the 1 "complete-version graph"), whereas for threshold equal to 100%, no node is protected with checkpoints (this is said to be the "original-version graph", and is shown in Fig. 1).…”

“…Along the last 30 years, CFC has become a widely studied and used approach for concurrent checking in microprocessor-based systems [1][2][3][4][5][6][7][8][9][10][11]. This type of on-line test is aimed at detecting sequencing errors during a program execution and are based on modifications of the application code where signatures are embedded and checked by the application processor (AP) [2][3][4]8] or by a watch-dog processor (WDP) [1,[5][6][7][9][10][11] against compilationtime pre-computed values every time the AP reaches these signature points.…”

“…This type of on-line test is aimed at detecting sequencing errors during a program execution and are based on modifications of the application code where signatures are embedded and checked by the application processor (AP) [2][3][4]8] or by a watch-dog processor (WDP) [1,[5][6][7][9][10][11] against compilationtime pre-computed values every time the AP reaches these signature points. These techniques are also known as Embedded Signature Monitoring (ESM).…”

“…For real-time embedded applications, system robustness is frequently achieved by means of hardware redundancy [1]. However, this solution results inevitably in more expensive systems.…”

New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors

“…To combine the benefits of software-based approaches with those of hardware-based ones, a hybrid fault detection solution was introduced in [9]. This technique combines the adoption of software techniques in a minimal version, for implementing instruction and data redundancy, with the introduction of an Infrastructure-Intellectual Property (I-IP) attached to the processor, for running consistency checks.…”