Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in memory arrays

Silva, Felipe; Freitas, Walter C.; Silveira, Jarbas; Marcon, César; Vargas, F.

doi:10.1016/j.microrel.2020.113582

Cited by 10 publications

(3 citation statements)

References 24 publications

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“…Silva et al [23] proposed an extended matrix region selection code (EMRSC) which increased correction capability and reduces the number of generated redundant bits by using data matrix regions. This method also generates a tradeoff between area and power overheads and reliability degree.…”

Section: Related Workmentioning

confidence: 99%

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

2021

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A new error detection and correction methodology, defined as Horizontal-Vertical-Diagonal-N-Queen-Parity (HVDNQ), is proposed in this paper. This approach relies on five different types of parities: horizontal parity, vertical parity, forward diagonal parity, backward diagonal parity, and queen parity. This method works on an N X N cell area and can correct multibit upsets. The experimental analysis validates the effectiveness of the proposed methodology by comparing its efficiency with existing methodologies. In different varieties of error patterns such as equilateral triangle, pentagon, hexagon etc., the capability of error detection and correction of HVDNQ is much better than existing methods.

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Section: Related Workmentioning

confidence: 99%

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

2021

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“…This type of ECC provides a low error correction rate, being suitable for environments that are not susceptible to faults and non-critical applications. However, critical applications running in environments that are more susceptible to faults demand more robust ECCs implemented with a more considerable redundancy overhead to achieve high error correction rates [30]- [33]. LPC belongs to this last class of ECCs, designed to increase significantly the ability to correct and detect errors.…”

Section: Lpc Format Considerationsmentioning

confidence: 99%

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This work introduces Line Product Code (LPC), a modified product code-based Error Correction Code (ECC) that uses both Hamming and parity in both rows and columns to implement reliable 3D memories. We implemented two lightweight LPC-based decoding algorithms in interleaved (LPCa-I) and non-interleaved (LPCa) versions, which allowed us to analyze LPC through a set of simulation cases that considers four severity levels of error incidence. The experimental results showed the effectiveness of the LPC-based algorithms, reaching correction rates of up 2.3 times higher compared to other Hamming-based algorithms.

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“…We performed the CDC analysis adapting the metric presented in [19], which considered the coverage of the proposed ECCs per the cost of the encoder and decoder. Our experiment does not consider the encoder cost since it is the same applied for all CLCs.…”

Section: B Correction Per Decoder Cost (Cdc) Analysismentioning

confidence: 99%

CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC

Silva

Muniz

Silveira

et al. 2020

2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI)

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Column-Line-Code (CLC) is an Error Correction Code (ECC) designed to correct multiple errors in memory devices for critical applications. CLC has originally two decoder modes: CLC Standard (CLC-S) and CLC Extended (CLC-E).CLC-E presents higher efficacy in correcting multiple errors, although consuming more area, dissipating more power, and presenting higher delay than CLC-S, which impacts the overall system performance. This paper proposes the CLC Adaptive (CLC-A), an alternative CLC mode that introduces a Syndrome Analyzer circuit, allowing the system to decide if a second error checking is required to correct the data. The experimental results show that CLC-A reaches higher error correction rates than CLC-S and similar values of CLC-E. Besides, CLC-A obtained nearly half the overhead in area and power and about 27% less delay when compared to CLC-E, which is a significant reduction in the synthesis cost.

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Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in memory arrays

Cited by 10 publications

References 24 publications

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity

LPC: An Error Correction Code for Mitigating Faults in 3D Memories

CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC

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