Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Abstract

Because of the today's market demand for highperformance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost.In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

Improved timing closure by analytical buffer and TSV planning in three-dimensional chips

“…Many interconnect optimization techniques have been proposed to reduce the delay of global wires such as driver sizing, buffer insertion, wire sizing, and spacing [1]. Buffer insertion is an effective and widely used technique to solve or alleviate the problem [2].…”

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

“…TSVs are high-density, low-capacitance interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between stacked dies, while operating at higher speeds and consuming less power [1]. TSV-based three-dimensional technologies enable the creation of a new generation of 'super chips' by opening up new architectural opportunities [20,38]. These so-called 3D Stacked ICs (3D-SICs) combine a smaller form factor and lower overall manufacturing costs [35] with many other compelling benefits, and hence their technology is quickly gaining ground.…”

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

“…A description of 3-D integration technologies and methods for 3-D thermal-aware floor-planning are presented in [1]- [5]. Router architectures, evaluations of regular NoC topologies, and thermal-aware mapping methods on NoC topologies for 3-D ICs are described in [21]- [23].…”