Extending the Applicability of Scalar Replacement to Multiple Induction Variables

Baradaran, Nastaran; Diniz, Pedro C.; Park, Joonseok

doi:10.1007/11532378_32

Cited by 9 publications

(7 citation statements)

References 4 publications

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“…Their work exploits full data reuse and does not address the issue of limited capacity from the perspective of reducing the iteration spaces by application of tiling and loop splitting. In our previous research, we have exploited the opportunities of scalar replacement by using both Block RAM and registers in FPGAs (Baradaran et al 2005). In this work, however, we did not exploit the space/performance trade-off associated with partial reuse using loop tiling and splitting.…”

Section: Related Workmentioning

confidence: 95%

“…Using data reuse analysis, a compiler tool can identify the reuse vector for scalar replacement (Baradaran, Diniz, and Park 2005), which is (0,1), (0,2) for the j loop in this example. Under specific loop bound conditions, it is possible to compute the number of registers required to exploit a specific reuse vector at compile time analysis, 6 registers in this case (So and Hall 2004).…”

Section: Motivating Examplementioning

confidence: 99%

“…The distance vector usually represented as a form of directed graph, called a reuse chain (So and Hall 2005). Details of the analysis to determine reuse vectors and distance vectors for single-induction-variable (SIV) and multiple induction variables (MIV) are described (Baradaran et al 2005).…”

Section: Data Reuse Analysis and Reuse Vectorsmentioning

confidence: 99%

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Partial data reuse for nested loop computations: design space exploration for FPGA implementations

Park

Diniz²

2008

International Journal of Electronics

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Automated compiler analyses and transformation techniques aim at improving design productivity of the mapping process of applications expressed in high-level programming languages to FPGAs. These transformations allow a compiler tool to reduce the number of design cycles and eliminate tedious and error-prone low-level transformations required in this mapping process, while still leading to good designs. Scalar replacement, also known as register promotion, is a very important data-oriented transformation that leads to designs that reduce the number of external memory accesses, and thus reduce execution time, at the expense of storage resource's. In this article we present a combination of loop transformation techniques, namely loop unrolling, loop splitting, and loop interchange with scalar replacement to enable partial data reuse on computations expressed by tightly nested loops pervasive in image processing algorithms. We describe a performance modelling in the presence of partial data reuse. Our experimental results reveal that our model accurately captures the non-trivial execution effects of pipelined implementations in the presence of partial data reuse due to the need to fill-up data buffers. The model thus allows a compiler to explore a large design space with high accuracy, ultimately allowing quickly it to find better designs than designs with limited manual search or brute-force approaches.

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Section: Related Workmentioning

confidence: 95%

Section: Motivating Examplementioning

confidence: 99%

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Partial data reuse for nested loop computations: design space exploration for FPGA implementations

Park

Diniz²

2008

International Journal of Electronics

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“…We leverage our previous work [Baradaran et al 2004] to identify the reusable data and compute the number of storage elements required to cache this data.…”

Section: Data Reuse Analysismentioning

confidence: 99%

“…To calculate the storage required to capture the data reuse associated with Chain r (either group-or self-reuse) we use the analytical expressions described in Baradaran et al [2004] and based on reuse vectors, arrays' index function, and loop bounds.…”

Section: Analysis Of Storagementioning

confidence: 99%

A compiler approach to managing storage and memory bandwidth in configurable architectures

Baradaran

Diniz

2008

ACM Trans. Des. Autom. Electron. Syst.

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Configurable architectures offer the unique opportunity of realizing hardware designs tailored to the specific data and computational patterns of an application code. Customizing the storage structures is becoming increasingly important in mitigating the continuing gap between memory latencies and internal computing speeds. In this article we describe and evaluate a compiler algorithm that maps the arrays of a loop-based computation to internal storage structures, either RAM blocks or discrete registers. Our objective is to minimize the overall execution time while considering the capacity and bandwidth constraints of the storage resources. The novelty of our approach lies in creating a single framework that combines high-level compiler techniques with lower-level scheduling information for mapping the data. We illustrate the benefits of our approach for a set of image/signal processing kernels using a Xilinx Virtex TM Field-Programmable Gate Array (FPGA). Our algorithm leads to faster designs compared to the state-of-the-art custom data layout mapping technique, in some instances using less storage. When compared to hand-coded designs, our results are comparable in terms of execution time and resources, but are derived in a minute fraction of the design time.

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Applied Reconfigurable Computing

Cardoso¹

2019

Lecture Notes in Computer Science

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Extending the Applicability of Scalar Replacement to Multiple Induction Variables

Cited by 9 publications

References 4 publications

Partial data reuse for nested loop computations: design space exploration for FPGA implementations

Partial data reuse for nested loop computations: design space exploration for FPGA implementations

A compiler approach to managing storage and memory bandwidth in configurable architectures

Applied Reconfigurable Computing

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