Extending value reuse to basic blocks with compiler support

Abstract

Speculative execution and instruction reuse are two important strategies that have been investigated for improving processor performance. Value prediction at the instruction level has been introduced to allow even more aggressive speculation and reuse than previous techniques. This study suggests that using compiler support to extend value reuse to a coarser granularity than a single instruction, such as a basic block, may have substantial performance benefits. We investigate the input and output values of basic blocks and find that these values can be quite regular and predictable. For the SPEC benchmark programs evaluated, 90% of the basic blocks have fewer than 4 register inputs, 5 live register outputs, 4 memory inputs and 2 memory outputs. About 16% to 41% of all the basic blocks are simply repeating earlier calculations when the programs are compiled with the-O2 optimization level in the GCC compiler. Compiler optimizations, such as loop-unrolling and function inlining, affect the sizes of basic blocks, but have no significant or consistent impact on their value locality, nor the resulting performance. Based on these results, we evaluate the potential benefit of basic block reuse using a novel mechanism called the block history buffer. This mechanism records input and live output values of basic blocks to provide value reuse at the basic block level. Simulation results show that using a reasonably-sized block history buffer to provide basic block reuse in a 4-way issue superscalar processor can improve execution time for the tested SPEC programs by 1% to 14% with an overall average of 9% when using reasonable hardware assumptions.

Compiler analysis for trace-level speculative multithreaded architectures

“…Program profiling analysis is an effective technique for determining code regions whose live-output values may be reused at run-time [7], [13]. In this paper we propose a profile-guided analysis for selecting the traces to be speculated by a TSMA processor.…”

“…A value prediction scheme guided by value profiling is presented in [10]. Compiler-directed approaches for identifying code regions whose computation can be reused during dynamic execution are proposed in [7] and [13]. A code specialization approach that uses value profiling is presented in [18].…”

Cascaded Window Memoization for Medical Imaging

“…The general concept of memoization in computer programs has been around for a long time where the idea is to speed up the computer programs by avoiding repetitive/redundant function calls [9] [10] [11]. Nevertheless, in practice, the general notion of memoization has not gained success due to the following reasons: 1) the proposed techniques usually require detailed profiling information about the runtime behaviour of the program which makes it difficult to implement [12], 2) the techniques are usually generic methods which do not concentrate on any particular class of input data or algorithms [13], and 3) the memoization engine used by these techniques are based on non-fuzzy comparison where two input data is considered equal (in which case one's result can be reused for another) if they are identical. In contrast, in designing the window memoization technique in [8], the unique characteristics of image processing algorithms have been carefully taken into account to enable window memoization to both be easy to implement and improve the performance significantly.…”

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

“…The reuse granularity includes instructions [15,20], expressions and invariants [13], basic blocks [9], traces [3,5], as well as instruction blocks and sub-blocks of arbitrary size [8] …”