Extensive evaluation of programming models and ISAs impact on multicore soft error reliability

Abstract

To take advantage of the performance enhancements provided by multicore processors, new instruction set architectures (ISAs) and parallel programming libraries have been investigated across multiple industrial segments. It is investigated the impact of parallelization libraries and distinct ISAs on the soft error reliability of two multicore ARM processor models (i.e., Cortex-A9 and Cortex-A72), running Linux Kernel and benchmarks with up to 87 billion instructions. An extensive soft error evaluation with more than 1.2 million simulation hours, considering ARMv7 and ARMv8 ISAs and the NAS Parallel Benchmark (NPB) suite is presented.

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

“…For instance, the average difference concerning executed instructions per core is around 4% considering MPI applications, while the OpenMP variation reaches up 16%. As the OpenMP does not fully utilise the available cores due to the fork/join parallelisation approach where a loop statement executes in parallel and other code portions hastily, corroborating the results presented in [14]. By contrast, the MPI has individual and independent working threads for each running core providing a better workload balance during its execution.…”

“…to the execution overhead of complex applications. A similar behaviour is also found in more complex scenarios [14], including more robust kernels, such as a Linux, executing multithread applications. One of the effects, of running the FreeRTOS or any OS is the occasional context switch, which overwrites the registers potentially masking dormant faults in the registers.…”

Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability

“…The growing susceptibility of multicore systems to soft errors necessarily calls for novel cost-effective tools to assess the soft error resilience of underlying systems early in the design phase. This paper employs two flexible fault injection (FI) frameworks, developed on the basis of two virtual platforms: OVPsim-FIM [16], and gem5-FIM [17]. The main difference between both FI frameworks is the simulation performance.…”

“…A fault injection campaign may comprise thousands of simulations, demanding a significant computational effort, which restricts the soft error analysis to small scenarios as reported in Section II. Developed simulation infrastructure (SI) includes a couple of features to boost up the fault injection simulation: checkpoint and distributed simulation [16,17]. 1) Checkpoint: A fault injection requires unnecessary code re-execution to provide the appropriated software context (i.e., fault injection time).…”

“…Further, the execution time of a single simulation ranges from 300 million to 86 billion instructions. Experiments were conducted considering an architectural level simulator (i.e., gem5) o inject faults in general purpose registers [17] because it is highly used by academics as well as accepted in many industrial sectors. Configurations including single, dual, quad, and octa-core ARM Cortex-A9 (ARMv7 Architecture) and Cortex-A72 (ARMv8) processors model with 1GB of memory RAM, and two-level cache memory configured as: L1 instruction and data 32kB 4-way associative, and L2 512kB 8-way associative.…”