External memory bist for system-in-package

Abstract

This paper presents the design and implementation of an External Memory Built-In Self-Test (BIST) in Systemon-Chip (SoC) designed for System-in-Package (SiP). We implemented the BIST handshaking with the internal bus in the microcontroller core for the purpose of enabling the BIST to access the CPU address space. This implementation allows to reduce the area overhead of the BIST and vary the test conditions flexibly according to each phase of debugging, reliability evaluation and massproduction test. For testing SDRAM and Flash, we also designed a microcode based algorithmic pattern generator with enough loop-counters, an infinite looping function and a multiple command sequence generator. This BIST method was applied to consumer products with the IEEE 1149.1 JTAG TAP controller, and enabled multitest for mass-production on a burn-in tester.

Design, Verification, and Application of IEEE 1687

“…For each of these scenarios, it is of interest to access some but not all of the instruments [7]. As an example, a memory built-in-self-test (MBIST) instrument might be accessed (1) during yield learning for a new process to choose the most suitable algorithms, (2) during wafer sort and package test to detect defective devices and perform repair, (3) in the burn-in process to cause activity in the chip and to detect infant mortality [8], [9], (4) during PCB bring-up [10], (5) during PCB assembly manufacturing test [10], and (6) during power-on self-test and in-field tests. Also, the number of accesses to a given instrument typically varies between different scenarios.…”

FPGA-based universal embedded digital instrument

“…For external memory, applications for testing these components exist within System-in-Package (SiP) with numerous abilities of debug [5] are being integrated into FPGAs. Another application of board-level BIST is testing high-speed I/O within ASICs to fully characterize AC parameters and debug faults [6].…”

A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory

“…The nonlinear instruction set can also support a simple dual-port memory test. The Column Output field (Inst [8]) selects the memory test column address between column counter X and column counter Y. In addition, multi-loop performance is supported by the nonlinear instruction set to more easily implement the non-March algorithm.…”

“…An Instruction Control field (Inst [13:12]) signifies the operational status so that the target test algorithm can be implemented. The Inst [8], Inst [7], Inst [6], and Inst [5] sets are used for multi-loop performance so that a complex address sequence can be generated for the non-March algorithms. The branch operation is performed through a branch register that also supports multiloop performance.…”