Extracting local don't cares for network optimization

Savoj, H.; Brayton, Robert K.; Touati, H.J.

doi:10.1109/iccad.1991.185319

Cited by 71 publications

(37 citation statements)

References 7 publications

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“…In [17], the CODC computation of [18] was shown to be dependent on the current implementation of a node, and an implementation-independent computation was proposed.…”

Section: I-b Previous Workmentioning

confidence: 99%

A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

Cobb

Gulati

Khatri

2010

Advanced Techniques in Logic Synthesis, Optimizations and Applications

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Multi-node optimization using Boolean relations is a powerful approach for network minimization. The approach has been studied in theory, and so far its superiority over single node optimization techniques has only been conjectured for practical designs. This is due to the highly memory intensive computations involved in the calculation of Boolean relations representing the multi-node optimization flexibility. In this thesis, an algorithm to perform Boolean relation-based multi-node optimization using a robust, fast and memory efficient algorithm is presented. In particular, two nodes are simultaneously optimized at a time. Results are reported on large designs, demonstrating the initial power of this multi-node optimization algorithm. The robustness of the approach arises from the use of a window-based technique for computing these Boolean relations. Secondly, aggressive early quantification is performed during the computation, keeping memory utilization low.Finally, smart heuristics are employed for selecting the node pair to be optimized simultaneously. These features allow the approach to scale well and provide good results for large designs. Experiments are performed on a set of large benchmarks and the algorithm's performance is compared to a SAT-based network optimization technique using complete don't cares. On average, the approach presented in this thesis achieves a 12% reduction in literal count across all the large designs compared to the complete don't cares, while maintaining small runtimes and low memory usage.

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“…In [17], the CODC computation of [18] was shown to be dependent on the current implementation of a node, and an implementation-independent computation was proposed.…”

Section: I-b Previous Workmentioning

confidence: 99%

A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

Cobb

Gulati

Khatri

2010

Advanced Techniques in Logic Synthesis, Optimizations and Applications

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“…The SPFD of a node/wire can be derived in a multitude of ways depending on its application during logic synthesis. For instance, SPFDs can be computed in a compatible fashion (similar to the compatible don't care computation [6]) from the primary outputs to the primary inputs [27]. In rewiring applications, the SPFD of a wire, (n a , n b ), can denote the minimum set of edges in the SPFD of n b that can only be distinguished by n a (but none of the remaining fanins of n b ) [27].…”

Section: Sets Of Pairs Of Functions To Be Distinguishedmentioning

confidence: 99%

“…A full-blown synthesis step may be a time-consuming and resource-intensive process for a design that needs only a few of structural changes. Furthermore, existing synthesis tools may significantly modify the structure of the design and jeopardize the engineering effort already invested in it [6], [7].…”

Section: Introductionmentioning

confidence: 99%

Automating Logic Transformations With Approximate SPFDs

Yang

Sinha

Veneris

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-During the VLSI design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate SPFDs and avoid the memory/time explosion issue inherent with the original representation. Then it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.

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“…Furthermore, it is not always clear from which part of a circuit the don't cares should be extracted. Various algorithms have been proposed to extract subsets of don't cares (see for example [68,69]). Optimization with don't cares has a close relation to other optimization methods, such as transduction [70], redundancy removal [10] and global flow analysis [71,72].…”

Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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Extracting local don't cares for network optimization

Cited by 71 publications

References 7 publications

A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations

Automating Logic Transformations With Approximate SPFDs

Integrated logic synthesis using simulated annealing

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