Extraction of channel mobility in nanowire MOSFETs using I<inf>d</inf>(Vg) characteristics and random telegraph noise amplitude

Abstract

Combined measurements of random telegraph noise of drain current and drain current -gate voltage characteristic are employed for determination of fieldeffect charge carrier mobility in surface channel of nanowire inversion mode and accumulation mode MOSFETs with taking into account parasitic sourcedrain resistance. IntroductionDetermination of charge carrier mobility in cannel of nanowire (NW) multigate (MuG) MOSFETs both inversión mode (IM) and accumulation mode (AM) operation is extremely complex task demanding knowledge of the geomentic sizes and gate capacitance of the devices. The gate capacitance of the NW MOSFETs does not yield to measurement because of their very small magnitude. Therefore a search of new methods and approaches are necessary to solve this task. In this paper we propose the combined measurements of the random telegraph noices (RTN) amplitude and drain current in dependence on applied gate voltage (RTNA(V g ), I d (V g )) on the same nanowire MOSFET for extraction of charge carrier mobility. The method is also applied to new type of multigate MOSFET, called the junctionless (JL) transistor, which has recently been proposed [1]. The device contains highly doped silicon wire with the pi-gate (Fig.1). The use of such a device avoids junction formation problem and can be used to make very short-channel devices [2]. Samples and MeasurementMultigate silicon NW n-type MOSFETs with pi-gate architecture were fabricated on UNIBOND ® silicon-oninsulator wafers (see Figures 1(a) and 1 (b)). The width and thickness of the devices is near 10 nm and the gate OHQJWK LV ȝP 7KH JDWH R[LGH DQG EXULHG R[LGH %2; thickness are 7 nm and 340 nm correspondingly. The JL MOSFET has uniform n-type doping concentration of 1x10 19 cm -3 in the source, drain and channel regions (Figure 1 (c)). "Standard" IM pi-gate MOSFET have the same dimensions as the JL devices but have a p-type channel doping concentration of 2x10 18 cm -3 and an ntype doping concentration of 1x10 20 cm -3 in the source and drain regions (Figure 1 (d)). The JL MOSFETs have a P + -polysilicon gate electrode and the IM devices have an N + -polysilicon gate.The I d (V g ) characteristics and RTN in drain current were measured by Agilent B1500A Semiconductor Parameter Analyzers. The RTNs were measured in sampling mode of the equipment operation. The RTNs were measured at gate voltage above the threshold voltage both of the IM and JL devices, which was determined by second derivative of the I d (V g ) characteristic. Fig.2 shows I d (V g ) characteristics, normalized transconductance (g m =dI d /dV g ) and transconductance deriviation (dg m /dV g =d 2 I d /dV g 2 ) vs. gate voltage for NW IM and JL MOSFETs measured at linear mode (V d = 50 mV). The transconductance deriviation allows us to Fig.1: Schematic view of architecture of the MOSFETs (a) and HRTEM photograph of the A-A section of the device (b). Schematic view of doping in the inversion-mode (c) and junctionless (d) n-channel devices. Results and Discussion

Triple-gate junctionless MOSFETs

“…where V th is the threshold voltage of accumulation which is replaced by the flat-band voltage. However, for bulk channel conduction in the JL MOSFET, the relation for I d /I d is complicated without following the (V gs -V th ) -1 dependence [43]. In the present work, in JL MOSFET operating in the gate voltage above the threshold voltage for bulk conduction, the relative RTN amplitude can be described with the g m /I d (V gs ) physicsbased model including the mobility fluctuation.…”

“… Low random telegraph-noise (RTN) and 1/f noise, an issue magnified in conventional Chapter 1: Introduction 12 devices, while maintaining full CMOS compatibility [43][44].…”

“…This has been explained considering that, even when the bulk neutral channel is separated by the depleted region, first diffusion through the depletion region and then tunneling can allow some mobile electrons from the bulk channel to interact with slow traps in the gate dielectric [131]. The investigation of the RTN amplitude of long channel JL MOSFET has been restricted in the accumulation mode of operation [43].…”

“…The dependence of ln( c / e ) on V gs has been also used to extract the trap position in the gate dielectric without taking into account the rate of change of the conductive path potential with the gate voltage at the trap position [43], which introduces large error in the estimation of the trap depth [173]. However, the lack of knowledge of the exact trap location along the channel does not allow the calculation of the conductive path potential at the trap position.…”

“…The RTN amplitude due to a single trap located at or near the gate dielectric/silicon interface in general is well described by the g m /I d (V gs ) trend. In [43], by neglecting the surface roughness scattering, the relative RTN amplitude in accumulation mode JL MOSFET has been described by the relation I…”