Extraction of Undetectable Faults in 6T- SRAM Cell

Maddela, Venkatesham; Sinha, Sanjeet Kumar; Parvathi, Muddapu

doi:10.1109/iccisc52257.2021.9484987

Cited by 3 publications

(2 citation statements)

References 20 publications

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“…The delayed release is caused by the VAST bit lines capacity and the limited access to the bit cell transistors. A slight discrepancy is broadened by the SA between the bit line voltages and the digital levels [76].…”

Section: Sense Amplifiermentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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This paper provides an overview of blockchain technology's security and privacy features, as well as an overview of IoT-based cache memory and single-bit six transistor static random-access memory cell sense amplifier architecture. Each chip's memory is used for recorded as blocks, which are encrypted and used as a blockchain for other memory devices. The architectures comprise of the circuit of write driver, six transistor static random access memory cells, and sense amplifiers such as current differential sense amplifier, charge transfer differential sense amplifier, and voltage latch sense amplifier. Furthermore, different parameters such as the number of transistors, sensing delay, and power consumption have been analyzed for varying resistance values (i.e., R=42.3 and R=42.3K ). Apart from that, power reduction techniques such as dual sleep, forced stack, sleep transistor, and sleep stack are used to optimize power consumption. These power reduction techniques are applied over different blocks of architecture, such as six transistors static random access memory cell and sense amplifier to optimize power consumption of the architecture. The conclusion arises that a single-bit six transistor static random access memory cell with power reduction dual sleep technique voltage latch sense amplifier with power reduction dual sleep technique in architecture consumes 11.65µW of power and has 33 transistors which are lowest from other architectures.INDEX TERMS Circuit of write driver (CWD), sense amplifier (SA), current differential sense amplifier (CDSA), charge transfer differential sense amplifier (CTDSA), voltage latch sense amplifier (VLSA), six transistor static random-access memory (6T-SRAM).

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Section: Sense Amplifiermentioning

confidence: 99%

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

et al. 2022

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“…The system experiences different impacts depending on how short or open defects between the nodes. The effect of such short/open faults on the behavior of deep submicron 6T-SRAM cells is explored in this work [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning

Maddela,

Sinha,

Parvathi

et al. 2024

Preprint

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In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. Many fault models have developed, however their flexibility of use is limited by the restrictions and constraints of the provided test environment. The majority of existing fault models have been studied in terms of well-known March algorithms, which simply provide fault detection information. Scaled-down technologies have an impact on parasitic effects as well, resulting in an extra source of defective behavior and making current test algorithms vulnerable to them. Recent work that uses method of parasitic extraction for fault detection have addressed the problem of limitation due to scale down technologies. However, as the circuit complexity increases the estimation of RC would be tedious. Hence in this paper machine learning based parasitic RC extraction is proposed. Also, as an extension to that, proposed ML based fault detection using extracted parasitic RCs as dataset. The proposed machine learning based fault prediction uses extracted parasitic RCs as dataset. The parasitic RC values are extracted for each fault model using technologies of 120nm down to deep submicron 7nm. Regression algorithm is used for modeling the machine for extraction of RCs and observed that 88% of prediction accuracy. Decision tree modeling is used for fault detection and observed 91.7% of accuracy in prediction of fault. 3.1 Effect of open defects in 6T SRAM Cell In this are article we have consider the node to node open/short faults. In Fig 2. We have imposed all possible open defects and then we have analyzed the memory cell for all possible open defects. There are totally 25 open defects are possible as shown in the fig 2. The simulation results and different types faults occurs for all open defects are shown in table 1 Fig2: Fault model for Open Defects in 6T-SRAM Cell Table 1. 6T SRAM Cell open defect list for different technologies

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SRAM Memory Testing Methods and Analysis

Parvathi

2023

Advances in Systems Analysis, Software Engineering, and High Performance Computing

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In the scenario of growing technologies towards single digit nanometer range, the existing algorithmic contemporary test methods have become inadequate in detecting all the faults within the static random access memory. To address the issues related to contemporary test methods, machine learning-based test analysis is proposed, which elevates the method of dataset preparation using various process parameters that are drawn from functional fault models (FFMs). The outcome of this proposed work is modeling of FFMs using ML regression, classification, and further prediction with accuracy analysis. The experiments resulted that logistic regression is best suited model that resulting with high accuracy in the range of 95% to 97%, compared to the linear regression model that results in accuracy levels in the range of 26.58% to 63%.

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Extraction of Undetectable Faults in 6T- SRAM Cell

Cited by 3 publications

References 20 publications

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Security and Privacy of Blockchain-Based Single-Bit Cache Memory Architecture for IoT Systems

Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning

SRAM Memory Testing Methods and Analysis

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