Extreme Learning Machine based Pattern Classifiers for Symbolic Interval Data

doi:10.5829/ije.2021.34.11b.17

Cited by 9 publications

(9 citation statements)

References 34 publications

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“…Investigation of various dielectric constants provide for an all-rounded knowledge of how the TFET responds towards different biomolecules towards development of customized designs in bioelectronic apparatuses. Figure 4 illustrates the variation of drain current against gate voltage in a given biomolecule (27).…”

Section: Resultsmentioning

confidence: 99%

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Buttol,

Balaji

2024

IJE

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This study introduces a biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor (DM-DMG TFET) in 10 nanometer technology. To detect diverse bio molecules, the biosensor incorporates a nano gap cavity formed through gate overlap on the drain side. The variation in ambipolar current serves as the sensing parameter, influenced by altering the dielectric constants of immobilized bio molecules within the nano cavity. In this paper, the simulation results of biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor with different dielectric constants imposed in nano cavity. A comprehensive examination of the biosensor's performance is conducted, exploring various positions and filling factors of bio molecules within the nano cavity region. This analysis involves a thorough investigation into the device's performance, considering a range of parameters such as drain current, electric field distribution, variations in surface potential, configurations of energy bands, behaviors of carrier concentration, and the Ion/Ioff ratio. The simulations are done using the Silvaco TCAD Atlas tool.

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Section: Resultsmentioning

confidence: 99%

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Buttol,

Balaji

2024

IJE

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“…The drain current (Id) versus gate-source voltage (Vgs) characteristics for a SDGTFET with variation of different technology regimes as shown in Figure 3 and investigate the proposed device characteristics scale with 10nm, 12nm and 15nm nodes (27). The 10nm node are scalable to smaller technology nodes for the limitations associated with scaling factor.…”

Section: Resultsmentioning

confidence: 99%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

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“…The simulation work is carried out with three different drain doping concentrations (Nd = 1 × 10 18 cm −3 , 2 × 10 18 cm −3 , and 3 × 10 19 cm −3 ) for the proposed device. Table 1 presents the values of the gate work function, gate-ondrain overlap work function, and equivalent oxide thickness beneath the gate-on-drain overlap for each of these drain doping concentrations (23). The channel length for all structures was set at 10 nanometers.…”

Section: Device Structure and Simulation Parametersmentioning

confidence: 99%

Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node

Howldar,

Balaji,

Srinivasa Rao

2024

IJE

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Extreme Learning Machine based Pattern Classifiers for Symbolic Interval Data

Cited by 9 publications

References 34 publications

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node

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