Extremely high mobility ultra-thin metal-oxide with ns2np2 configuration

Shih, C. W.; Chin, Albert; Lu, Chih-Hung; Yi, S. H.

doi:10.1109/iedm.2015.7409642

Cited by 15 publications

(19 citation statements)

References 8 publications

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“…Increasing the annealing temperature from 100 to 400 °C led to significant Sn diffusion from SnO into HfO2. This is attributed to the weak Sn-O band enthalpy [38], even though it also leads to high hole mobility [15,16]:…”

Section: Resultsmentioning

confidence: 99%

“…Thus, the higher post-annealing temperature will cause more inter-diffusion between HfO2 and SnO. [38], even though it also leads to high hole mobility [15,16]: The diffused Sn 2+ can behave as trap states in HfO2 gate dielectric, provide extra transport paths for the carriers, and lead to higher gate leakage current (Figure 4b). To understand the conduction mechanism of gate leakage current, the measured data were fitted with various mechanisms.…”

Section: Resultsmentioning

confidence: 99%

“…Metal-oxide Thin film transistors (TFTs) have drawn considerable attention due to their high mobility, low fabrication temperature, and simple fabrication process, making them suitable for advanced display [1][2][3][4][5][6] and monolithic three-dimensional (3D) integrated circuit (IC) [15][16][17][18][19][20][21] on amorphous inter-metal-dielectric (IMD) of a Si chip. To reach low DC power consumption, both high performance n-and p-type TFTs are necessary to form the complementary metal-oxide-semiconductor (CMOS) logic.…”

Section: Introductionmentioning

confidence: 99%

“…To reach low DC power consumption, both high performance n-and p-type TFTs are necessary to form the complementary metal-oxide-semiconductor (CMOS) logic. Although high-performance n-TFTs with high field-effect mobility (µ FE ), sharp subthreshold swing (SS), and large on-current/off-current (I ON /I OFF ) values [12][13][14][15] have been reported, achieving reasonable performance p-TFTs is much more challenging [16,17,36,37]. Moreover, a top-gate structure is more suitable than a conventional bottom-gate device for high integration density and easy fabrication [24][25][26].…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, the weak Sn-O bond enthalpy [38] facilitates Sn diffusion into high-dielectric-constant (high-κ) HfO 2 insulator at elevated temperature, 2 of 11 thus degrading device performance. In this study, the above challenges were successfully overcome, and high-performance top-gate nanosheet SnO p-TFT was achieved with high µ FE of 4.4 cm 2 /Vs, large I ON /I OFF of 1.2 × 10 5 , and sharp SS of 526 mV/decade, indicating a high potential for future monolithic 3D and brain-mimicking IC applications [15,[17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

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Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

2021

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Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

2021

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Outstanding High Field‐Effect Mobility of 299 cm² V⁻¹ s⁻¹by Nitrogen‐Doped SnO₂Nanosheet Thin‐Film Transistor

Pooja

Chun

Zeng

et al. 2023

Adv Materials Technologies

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Record high field‐effect mobility (µFE) thin film transistors (TFTs) based on 5 and 7 nm thickness SnON channel layer is reported. The SnON TFT device with 7.6% nitrogen content achieves a record high µFE of 299 cm2 V−1 s−1 at 7 nm thickness and 277 cm2 V−1 s−1 at 5 nm thickness, compared to SnO2 with µFE of 211 cm2 V−1 s−1. At the same 5 nm quasi‐2D channel thickness, this µFE of nanocrystalline SnON transistor is comparable to single crystalline Si and InGaAs metal oxide semiconductor field‐effect transistor (MOSFET) and also higher than the phonon‐scattering‐limited 2D MoS2 FET. From the principle of quantum‐mechanical calculation, the high µFE of nanosheet SnON TFT is due to lower effective mass of electrons, 0.29 m0 in the conduction band in contrast to 0.41 m0 of SnO2. SnON can reduce the defect trap densities by introducing non‐oxide anions where the valence band can be controlled to remove or passivate the oxygen vacancy levels by substitutional alloying with nitrogen anions to circumvent instability, increase on‐current (ION) and improve the µFE. It is highly expected that the high performance quasi‐2D nanosheet SnON TFTs will be utilized in embedded DRAM and monolithic 3D integrated circuits (ICs).

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43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

Chin

Yen

Chen

et al. 2021

Symp Digest of Tech Papers

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One technology bottleneck for system‐on‐panel (SoP) is the lacking of high‐performance p‐type thin‐film transistor (pTFT). Using high dielectric‐constant (high‐κ) gate materials with optimized processes, high hole and electron field‐effect mobility of 7.6 and 345 cm2/Vs were measured in pTFT and nTFT, respectively. These high mobility devices on SiO2 are the enabling technology for SoP and crucial for three‐dimensional brain‐mimicking integrated circuit (IC)‐ the technology trend for IC after reaching the quantum‐mechanical limit soon.

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Extremely high mobility ultra-thin metal-oxide with ns2np2 configuration

Cited by 15 publications

References 8 publications

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Outstanding High Field‐Effect Mobility of 299 cm² V⁻¹ s⁻¹by Nitrogen‐Doped SnO₂Nanosheet Thin‐Film Transistor

43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

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Extremely high mobility ultra-thin metal-oxide with ns2np2 configuration

Cited by 15 publications

References 8 publications

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Outstanding High Field‐Effect Mobility of 299 cm2 V−1 s−1by Nitrogen‐Doped SnO2Nanosheet Thin‐Film Transistor

43.2: Invited Paper: High Mobility Oxide Complementary TFTs for System‐on‐Display and Three‐Dimensional Brain‐Mimicking IC

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Outstanding High Field‐Effect Mobility of 299 cm² V⁻¹ s⁻¹by Nitrogen‐Doped SnO₂Nanosheet Thin‐Film Transistor