Extremely low surface recombination velocities on crystalline silicon wafers realized by catalytic chemical vapor deposited SiNx/a-Si stacked passivation layers

Abstract

Articles you may be interested inDrastic reduction in the surface recombination velocity of crystalline silicon passivated with catalytic chemical vapor deposited SiNx films by introducing phosphorous catalytic-doped layer

Construing the interaction between solar cell surface and fatty amine for the room temperature passivation

“…In these passivation schemes, the processes require high temperatures between 100°C and 1000°C for obtaining a high quality passivating layers (Aberle, 2000;Wenham et al, 2001;Lee and Glunz, 2006;Bousbih et al, 2012;Pudasaini et al, 2013aPudasaini et al, ,b, 2014Davis et al, 2013), amounting significant energy input toward solar cell fabrication. The aforementioned demand of high temperature is also detrimental for quality of the bulk Si apart from increase in the upfront costs of solar cell (Koyama et al, 2010;Yang et al, 2013).…”

Drastic reduction in surface recombination velocity of crystalline silicon by surface treatment using catalytically-generated radicals

“…The reason for using such thick a-Si films, which seriously absorb incident light, is that we focus on investigating SRVs at a-Si/c-Si interfaces in this study. The utilization of extremely thin a-Si films results in the tunneling of carriers through a-Si films and their frequent recombination on a-Si surfaces [7,8], which should be avoided for the precise estimation of SRVs at a-Si/c-Si interfaces. For practical application, another passivation layer, such as Si nitride (SiN x ), will be deposited on thin ( $ 10 nm) a-Si films.…”

High quality crystalline silicon surface passivation by combined intrinsic and n-type hydrogenated amorphous silicon

“…At annealing temperatures between 210 C and 270 C, very high carrier lifetimes, in excess of 10 ms at 10 15 cm À3 , are obtained, peaking at 255 C. The minority carrier lifetime at this temperature is equal to s eff ¼ 13.3 ms at 10 15 cm À3 ; superior to values reported thus far in the literature for c-Si passivated by a-Si:H. The injection level dependent minority carrier lifetime of this sample is shown in Figure 2. Other high lifetimes by a-Si:H containing layer stacks have, for instance, been obtained by Koyama et al 15 for layer stacks consisting of a-Si:H and a-SiN x :H deposited by hot-wire CVD (9.7 ms at 10 15 cm À3 ). For intrinsic a-Si:H, lifetimes around 10 ms at 10 15 cm À3 have been obtained by the authors of this work, 8 as well as by De Wolf et al 16 As can be seen from Figure 3, we measured even higher minority carrier lifetime values at lower injection levels (exceeding 15 ms for injection levels below 1.5 Â 10 14 cm À3 ).…”