Extremely- Scaled Channel Thickness ZnO FET with High Mobility 86 cm²/V-s, Low SS of 83mV/dec and Low Thermal Budget Process (<300°C)

Review—Extremely Thin Amorphous Indium Oxide Transistors

“…Shaded areas represent the most desirable regions of device operation for logic transistors. Data sources: indium oxide, [106,[110][111][112][113] ITO, [100,142,99] IGZO, [143][144][145][146]97] IWO, [102,135] ZnO, [147] MoS 2 , [148][149][150][151][152][153][154][155][156] WS 2 , [157][158][159][160] Te, [161] WSe 2 , [162] black phosphorus, [163][164][165] GaN, [166] InGaAs, [167] InAs, [168] Si. [116] conditions [110] with disadvantages in process maturity, geometry (planar versus fin), and device scaling (40 nm channel length versus the 4 nm-equivalent node).…”

“…In oxides that tend to crystallize, the extreme thinness can promote amorphization to reduce grain boundary issues, and in oxides that tend to degenerate like indium oxide and ITO the extreme thinness can reduce the carrier concentration to a manageable level that can be controlled effectively by electrostatic gating. In addition to pure indium oxide, work in this area has been reported in IGZO, [96,97] ITO, [100,98,99] indium tungsten oxide (IWO), [101,102] zinc oxide, [103] titanium oxide, [104] indium aluminum zinc oxide (IAZO), [105] with record-level performance frequently being reported after thickness scale-down. For indium oxide, functional devices have been fabricated with layers as thin as 0.5 nm, [106] but the best performance is generally found at between 1.2 and 3.5 nm thick in the established process.…”

“…Shaded areas represent the most desirable regions of device operation for logic transistors. Data sources: indium oxide, [ 106,110–113 ] ITO, [ 100,142,99 ] IGZO, [ 143–146,97 ] IWO, [ 102,135 ] ZnO, [ 147 ] MoS 2 , [ 148–156 ] WS 2 , [ 157–160 ] Te, [ 161 ] WSe 2 , [ 162 ] black phosphorus, [ 163–165 ] GaN, [ 166 ] InGaAs, [ 167 ] InAs, [ 168 ] Si. [ 116 ]…”

Heterogeneous Integration of Atomically‐Thin Indium Tungsten Oxide Transistors for Low‐Power 3D Monolithic Complementary Inverter

“…For BEOL compatible materials, the p-channel polycrystalline silicon (poly-Si) and nchannel amorphous oxide semiconductor (AOS) with closer and higher carrier mobility provide a solution for the compatibility issues. [5][6][7][8][9] This hybrid integration circuit provides the promising potential in low power dissipation due to its complementary configuration and the low leakage current in wide energy bandgap AOS. The hybrid complementary inverter composed of poly-Si and amorphous indium zinc gallium oxide (a-IGZO) had been proposed, performing the high gain and full swing properties.…”

High-Performance Top-Gated and Double-Gated Oxide–Semiconductor Ferroelectric Field-Effect Transistor Enabled by Channel Defect Self-Compensation Effect

“…M ONOLITHIC 3-D (M3-D) integration of reconfigurable nonvolatile logic circuits can enable ultraenergyefficient 3-D ICs by bringing memory elements closer to compute components and providing highly flexible system run-time reconfiguration capabilities that are difficult to achieve solely with conventional VLSI [1], [2], [3], [4]. Growing reports have also shown that oxide-semiconductors, such as amorphous indium-gallium-zinc-oxide (IGZO), can replace the conventional silicon (Si)-based transistor channel [5], [6], [7], [8]. This offers exciting M3-D integration possibilities that overcome the back-end-of-line (BEOL) low-k/Cu low thermal-budget process constraints owing to its low-temperature process, excellent wafer-scale deposition uniformity, and modestly high electron mobility [9].…”