Extrinsic equivalent circuit modeling of InP HEMTs based on full-wave electromagnetic simulation

Abstract

With the widespread utilization of indium-phosphide-based high-electron-mobility transistors (InP HEMTs) in the millimeter-wave (mmW) band, the distributed and high-frequency parasitic coupling behavior of the device is particularly prominent. We present an InP HEMT extrinsic parasitic equivalent circuit, in which the conductance between the device electrodes and a new gate–drain mutual inductance term L mgd are taken into account for the high-frequency magnetic field coupling between device electrodes. Based on the suggested parasitic equivalent circuit, through HFSS and advanced design system (ADS) co-simulation, the equivalent circuit parameters are directly extracted in the multi-step system. The HFSS simulation prediction, measurement data, and modeled frequency response are compared with each other to verify the feasibility of the extraction method and the accuracy of the equivalent circuit. The proposed model demonstrates the distributed and radio-frequency behavior of the device and solves the problem that the equivalent circuit parameters of the conventional InP HEMTs device are limited by the device model and inaccurate at high frequencies when being extracted.

A distributed small signal model extraction method based on FW-EM simulation for InP HEMT

“…And the parasitic parameters are more complex, making it less applicable to extract multiple parasitic capacitances using the traditional approach. Therefore, there are two main extraction strategies are proposed, including hybrid extraction method [15,16,17,18,19] and FW-EM simulation [14,20,21,22,23,24,25,26,27]. The hybrid optimization technique determines the starting values from measurements and then uses a local optimization technique to find the optimal value of each parameter.…”

“…However, it can not achieve direct extraction of inductance using FW-EM simulation. A direct extraction method introduced by using six dummies, but it might possess a problem of overestimating the value of the gate parasitic inductance, resulting in a negative value of the source parasitic inductance due to the design of the standard Thru1 and Thru2 [25,26,27]. Furthermore, because ohmic contacts as well as metal electrodes contribute to the parasitic resistances of the source and drain, straightforward use of FW-EM simulation to explain parasitic resistances is insufficient.…”