Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

Abstract

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40µA/µm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressedat the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decadewas obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application. INDEX TERMS TFET Ge PAI, line tunneling, cryogenic temperature.

Design and Performance Investigation of a Source Pocket-Based Charge Plasma TFET with Gate Underlap Technique

“…The authors fabricated a charge plasma diode considering the work-function difference between the metal contact and the intrinsic silicon body. Similarly, Cheng et al proposed the fabrication of a pocket in the source region of TFET, 33 which confirms the fabrication possibility of the suggested device. However, the step-by-step fabrication flow of SP-CPTFET is shown in Fig.…”

Tunneling towards efficiency: A survey of design and optimization strategies for tunnel FETs in ultra-low power applications

“…On this basis, [9] details the selection of specific materials in the channel region, such as group III-V semiconductors, InAs or GaSb, and points out their significant impact on the tunneling probability and current. The discussion of the importance of material selection for optimizing TFET performance is further extended in [13], which examines materials such as III-V compound semiconductors, germanium, nanowires, and carbon-based nanomaterials as potential solutions to the low ion limitation challenge of TFETs.…”

“…In classifying isolation and implantation techniques, Cheng et al, offer noteworthy methods for silicon-based TFETs [13]. It employs Local Oxidation of Silicon (LOCOS), P-well, and fluorine and molecular boron difluoride (BF2) implantations along with Ge pre-amorphization implantation (PAI) combined with ultra-low energy implantation.…”

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

“…At such scaled nano‐dimensions, especially for heterojunction designs, studies on the design reliability aspects become essential; 2,6,16,17,22,23 however, not much work has been that in that respect. Further, designs particularly based on SiGe/Si line tunneling heterojunctions 7‐14 that have been actually demonstrated till now adhere to fabricated Si pockets lying in the range of 6‐7 nm, 7,10 with the very recent gate‐normal TFET comprising a relaxed ~10 nm line pocket 9 . Further, circuit level studies have revealed a potential for excellence; 13 however, at the cost of very high overshoots/undershoots 14 …”

“…Therefore, counter‐doped line horizontal pockets (HPs) below gates were reported, which reduced the high onset voltage requirements as well as the gate variability effects 3 . Since then, line TFETs based on ultra‐thin pockets have gained popularity 4‐20 …”