Fabrication and characterization of copper interconnects of line-width down to 100nm using a specially designed phase shift mask

Reaction temperature and time dependence of MoCl5 intercalation to few-layer graphene

“…[1][2][3] The narrow line widths below 10 nm is required for the LSI interconnects of 3 nm node and beyond. [3][4][5][6] However, the increase of Cu interconnect resistivity and the degradation of EM reliability are found to be serious issues after scaling down width below 40 nm. 3,5,7,8) The high current capacity and robustness against EM of graphene have been expected for nanointerconnect applications.…”