Fabrication and Characterization of Novel Oxide-Free InP Metal-Insulator-Semiconductor FETs Having an Ultra Narrow Si Surface Quantum Well

Abstract

A novel oxide-free InP metal-insulator-semiconductor field-effect transistor (MISFET) with an ultra narrow Si surface quantum well in the gate structure was proposed and fabricated. The ultra thin Si 3 N 4 /Si interface structure was realized by molecular-beam epitaxy (MBE) growth and partial nitridation of a pseudomorphic Si interface control layer (Si ICL) on an InP epitaxial layer. Passivation effect of the InP surface was monitored in situ by X-ray photoelectron spectroscopy (XPS) and ultrahigh vacuum (UHV) contactless capacitance-voltage (C-V ) methods. A strong surface passivation effect was achieved after partial nitridation of the Si ICL with an optimal nitridation time. The fabricated MISFET with the Si-ICL passivation exhibited excellent gate control capability and stable operation. The drift of the drain current was found to be as small as 1.9% after 10 4 s operation.

Effects of gap states on scanning tunneling spectra observed on (110)- and (001)-oriented clean surfaces and ultrathin Si layer covered surfaces of GaAs prepared by molecular beam epitaxy

“…1͑b͒, if the ICL thickness is of the few monolayer level. The effectiveness of this method has been demonstrated in a macroscopic way in various device-oriented structures including InGaAs and InP insulated gate field effect transistors ͑IGFETs͒ and high electron mobility transistors ͑IHEMTs͒, [3][4][5] AlGaAs/GaAs near-surface quantum wells, 6 and InAlAs/InGaAs near-surface ridge quantum wires. 7 However, from the microscopic point of view, the mechanism for Fermi level pinning on III-V surfaces and its reduction by the Si ICL is not well understood.…”

Optimization and Interface Characterization of a Novel Oxide-Free Insulated Gate Structure for InP Having an Ultrathin Silicon Interface Control Layer

“…In spite of this, the device having a new gate structure with an InGaAs cap layer showed a high g m of 123 mS/mm and a high drain current level of 389 mA/mm. As compared with the previous InP MISFETs without the InGaAs cap layer 11) , the g m value was enhanced by a factor of 4. We believe that this is due to the improvement of the interface properties of the modified insulated gate structure.…”

Surface passivation of epitaxial multilayer structures for InP‐based high‐speed devices by an ultrathin silicon layer

“…In the model-solid theory, the strain is divided into hydrostatic and share components. The band edge shifts ∆E V (static) and ∆E C (static) of the valence and conduction bands due to the hydrostatic strain are given by where a V and a C are the deformation potentials for the valence and conduction bands, respectively, and c 11 , c 12 , and c 44 are elements of the strain tensor for the (001) plane. In the case of the valence band, the shifts of heavy holes, light holes, and split-off bands are given by …”

“…To reduce surface states and remove the Fermi level pinning, our group proposed a novel ultrathin silicon interface control layer (Si ICL)-based surface passivation method [6][7][8] and its capability has been confirmed through scanning tunnel spectroscopy (STS) of GaAs surfaces, enhancement of the photoluminescent intensity from AlGaAs/GaAs near surface quantum wells [10], and the successful fabrication and characterization of InGaAs [11] and InP [12] metal-insulator-semiconductor FETs (MISFETs).…”