Fabrication, Boron Leaching, and Electrochemical Impedance Spectroscopy of Nanoporous P-Type Silicon

Mebed, Abdelazim M.; Malsche, Wim De; Abd‐Elnaiem, Alaa M.

doi:10.1007/s12633-021-01338-3

Cited by 4 publications

(1 citation statement)

References 66 publications

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“…Since the macropore fabricated on n-type silicon was first reported in 1970's [1], it has attracted great attention for many applications, such as photonic crystals [2][3][4][5][6], field effect transistors (FETs) [7,8], high-density silicon capacitors [9][10][11][12][13][14], templates [15], through silicon vias [16,17], microneedles [18][19][20][21], microfluidics [22,23], heat sinks [24], neutron detectors [25,26], and so on. Among all of them, the crucial problem is to fabricate controllable and homogeneous macropore arrays, especially for high-aspect-ratio ordered macropores.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of Ordered Macropore Arrays in n-Type Silicon Wafer by Anodic Etching Using Double-Tank Electrochemical Cell

Zhang,

et al. 2024

Micromachines

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In this work, ordered macropore arrays in n-type silicon wafers were fabricated by anodic etching using a double-tank electrochemical cell. The effects of the wafer thickness, etching time and voltage on the quality of macropore arrays were investigated. Homogeneous macropore arrays could be achieved in 200 μm thick silicon wafers, but could not be obtained from 300 and 400 μm thick silicon wafers. Highly ordered macropore arrays with an aspect ratio of 19 were fabricated in 200 μm thick n-type silicon at 4.5 V. The etching current decreases in 200 μm thick silicon but increases in thicker silicon with an increase in time. It demonstrates that the minority carrier transportation capability from the illuminated surface to the reactive surface is different for silicon wafers with different thicknesses. The minority carrier concentration at the illuminated surface for stable macropore formation and the current under different etching voltages were calculated based on a hole transport model. The results show that appropriately decreasing wafer thickness and increasing voltage can help stable macropore array fabrication in the illumination-limited double-tank cell.

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