2010
DOI: 10.1063/1.3284952
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Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situ method and its effective work function modulation of metal/high-k stacks

Abstract: Lanthanum (La) incorporation into Hf-silicate high-permittivity (high-k) gate dielectrics was conducted using a physical-vapor-deposition (PVD)-based in situ method. PVD-grown metal Hf, La, and Hf–La alloys on base SiO2 oxides received in situ annealing to form high-quality HfLaSiO dielectrics, and subsequent deposition of metal gate electrodes was carried out to fabricate advanced metal/high-k gate stacks without breaking vacuum. The in situ method was found to precisely control La content and its depth profi… Show more

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Cited by 13 publications
(10 citation statements)
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“…[4][5][6] Our previous study, focusing on the La-induced interface dipole in TiN/HfLaSiO/SiO 2 /Si gate stacks, showed the upward diffusion of La at temperatures above 900 C, at which point the SiO 2 underlayer thickness increased. 7 On the basis of this result, we speculated that the upward diffusion is driven by SiO 2 growth and can thus be suppressed by hampering this growth. Since a metal inserted polycrystalline silicon (poly-Si) stack (MIPS) structure can suppress SiO 2 growth during high-temperature annealing, 8,9 we considered MIPS structure as an enabler to suppress the upward diffusion.…”
mentioning
confidence: 87%
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“…[4][5][6] Our previous study, focusing on the La-induced interface dipole in TiN/HfLaSiO/SiO 2 /Si gate stacks, showed the upward diffusion of La at temperatures above 900 C, at which point the SiO 2 underlayer thickness increased. 7 On the basis of this result, we speculated that the upward diffusion is driven by SiO 2 growth and can thus be suppressed by hampering this growth. Since a metal inserted polycrystalline silicon (poly-Si) stack (MIPS) structure can suppress SiO 2 growth during high-temperature annealing, 8,9 we considered MIPS structure as an enabler to suppress the upward diffusion.…”
mentioning
confidence: 87%
“…The thickness of the deposited metal Hf was 0.5 nm and PDA treatments were carried out in a vacuum (base pressure was less than 5.0 Â 10 À4 Pa) followed by FGA. 7 Figure 3(a) shows the relationship between EOT and J g after PDA treatments (at 600, 700, 800, and 900 C) for the samples with 5-nm-and 100-nm-thick TiN gate electrodes together with their linear fit. For both TiN thicknesses, the EOT increased as annealing temperature increased.…”
mentioning
confidence: 99%
“…The physical and electrical properties of La-incorporated Hf-based oxides, such as HfLaO and HfLaSiO, are crucially dependent on their La concentration and thermal treatment condition. Actually, one of the current authors (Arimura) toward the SiO 2 underlayers under moderate annealing condition, and the anomalous La outer-diffusion toward the high-k surfaces caused by high-temperature annealing over 900 C. 12 In addition to the threshold voltage control, the electronic structure of Hf-based oxides ought to be affected by La addition. The band-edge electronic structure of the dielectric material is important for predicting and designing the band diagrams of high-k gate stacks.…”
Section: Introductionmentioning
confidence: 98%
“…4) Incorporating lanthanum (La) into Hf-based oxides is effective in V th tuning for n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) due to the dipole formation at the high-k/SiO 2 interface. [6][7][8] Recent firstprinciples calculations revealed that La incorporation is beneficial for suppressing V O formation in Hf-based oxides. 9) Previously, La-incorporated high-k transistors have been demonstrated in the aim for low-V th high-performance nMOSFETs with the gate-first process.…”
Section: Introductionmentioning
confidence: 99%