Fabrication of nanocrystal memories by ultra low energy ion implantation

Abstract

In silicon nanocrystal based metal-oxide-semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work, we show how to manipulate and control the depth-position and the density of 2D arrays of Si ncs embedded in thin (<10 nm) SiO 2 layers, fabricated by ultra-low energy (typically 1 keV) ion implantation. It is demonstrated that the injection distance between the ncs band and the channel can be tuned from 10 to 2 nm by a judicious combination of ion beam energy and initial SiO 2 thickness. Annealing under slightly oxidizing ambient has been found essential for the optimization of the memory properties of the devices. During such oxidations, the oxide integrity is restored, the ncs are passivated and a separation of connected ncs takes place, making possible a further increase of the ncs density and a decrease of their mean size. . The use of isolated Si clusters instead of continuous poly-Si layer decreases the overall coverage that weakens current leakage through underlying tunnel oxide by defect paths. It opens the promising way to continue scaling-down tunnel oxide and thus, to fabricate high-chargedensity low-power-consuming devices. That is definitely required in such direct tunnelling regime is a fine control of the nanocrystal location since a change of less than 1 nm in tunnel oxide thickness dramatically affects programming properties (write/erase times and voltages) and data retention [2,3]. Among different deposition techniques [1,4], like thermal oxidation of Si 1-x Ge x [5] or ion implantation followed by annealing [6] used for the performance of nanocrystal memories, ultra-low energy Si implantation and subsequent thermal treatment has been recently demonstrated [7][8][9] to be the most attractive one. But up to now no systematic studies of ncs formation processes have been performed. In this work, we show how to manipulate and control the depth-position and the density of 2D arrays of Si ncs embedded in thin (<10 nm) SiO 2 layers, fabricated by ultra-low energy (typically 1 keV) ion implantation. Specific experimental methods have been developed to characterize these populations of ncs. They

Imaging Si nanoparticles embedded in SiO2 layers by (S)TEM-EELS

“…This fabrication route is very attractive because of its ability to control the size and location of the narrow nps band and its compatibility with standard CMOS technology. In practice, high-dose (typically 10 16 cm À2 ) Si implantation in the 1 keV range into very thin (up to 10 nm thick) oxide layers followed by annealing (900-1000 1C), allows for the formation of two-dimensional arrays (2D-arrays) of Si nps positioned at direct tunneling distances from the SiO 2 /Si interface [5].…”