1989
DOI: 10.1109/20.92842
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Fabrication of Nb/Al-Al/sub 2/O/sub 3//Nb junctions with extremely low leakage currents

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Cited by 59 publications
(15 citation statements)
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“…The junction capacitance is determined from the junction size obtained by SEM-observation of the test junctions. We use a capacitance to surface ratio of 48 fF/µm 223, 24 . …”
Section: Experiments a Samplementioning
confidence: 99%
“…The junction capacitance is determined from the junction size obtained by SEM-observation of the test junctions. We use a capacitance to surface ratio of 48 fF/µm 223, 24 . …”
Section: Experiments a Samplementioning
confidence: 99%
“…It may be expected, that SNEP (Selective Niobium Etching Process) affects the sub-gap current to a lesser extent, which would explain the high value of V, in ref. 1.…”
Section: Discussionmentioning
confidence: 99%
“…Our best explanation for why single resist processing worked now after being abandoned for a multi-layer resist process before can be attributed to the photoresists used in processing. The current process succeeds using a negative resist, optimized for high temperature use and liftoff, whereas the single resist used in the past was a resist modified with a chlorobenzene dip to create an overhang preferable for liftoff [7]. The question of why elements smaller than ~1.5µm have resistive or point contact electrical characteristics remains unsolved at this time.…”
Section: Chapter Two: Single Resist Processingmentioning
confidence: 99%
“…This is the most critical processing step for creating SIS devices, requiring precise definition of the junction area, but it is also demanding of the SiO2 layer. The concept of using a multi-layer resist for creating junctions started for this group with the fabrication of micron sized Nb/Al-Al2O3/Nb Junctions with a trilevel resist liftoff process [7,8]. This process replaced the previously used single resist approach that utilized a combination of anodized Nb2O5, formed from the exposed niobium, along with evaporated SiOx for the insulation layer encircling the device junctions and between the M1 base electrode and M3 wiring layers.…”
Section: Chapter One: Sis Insulation Applicationsmentioning
confidence: 99%
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