Fabrication of optically smooth, through-wafer silicon molds for PDMS total internal reflection-based devices

Abstract

This paper presents a systematic approach to fabricate optically smooth, through-wafer silicon (Si) molds for polymer optical devices, in particular poly(dimethylsiloxane) (PDMS) total internal reflection (TIR)-based devices. First, the Si molds were fabricated by an optimized, through-wafer deep reactive ion etching (DRIE) process to achieve small roughness. To further reduce the roughness, the Si molds were then oxidized and etched in BHF for three times to achieve surface roughness average (R a ) and root mean square (RMS) roughness below 25 nm while peakto-valley (P-V) roughness is below 150 nm. We monitored the surface roughness and morphology of the sidewalls of Si mold through three cycles of oxidation and BHF etching using field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM). We found that further oxidation and BHF etching might not have much effect in further reducing the roughness while the device feature definitions might be compromised. Finally, the PDMS TIR-based devices replicated from the Si molds were evaluated by means of FESEM, AFM and by imaging of the fluorescent evanescent spots.

A Monolithic Dual-Color Total-Internal-Reflection-Based Chip for Highly Sensitive and High-Resolution Dual-Fluorescence Imaging

“…We further reduced the roughness of the Si molds by three cycles of oxidation (the SiO 2 thicknesses were 370, 230, and 230 nm, respectively) and BHF etching [ Fig. 7(e)] [35]. The SiO 2 growth has been shown to depend greatly on the feature geometry, meaning that convex corners grow faster than concave corners [36].…”

Sacrificial structures for deep reactive ion etching of high-aspect ratio kinoform silicon x-ray lenses

“…For example, if permissible, shape-defining trenches may be completely etched through a silicon wafer, releasing material that was completely surrounded by trenches. [18][19][20] Wafers may become too fragile for further handling and/or need to be stabilized in an additional process step prior 21 or subsequent 20 to throughetching. Alternatively, more expensive silicon-on-insulator substrates combined with notching may be used, which occurs during DRIE once the buried oxide layer is exposed.…”

Design and fabrication of micro-coils for NMR micro probes

“…However in this case, Le et al combined 3 techniques (viz. careful design, optimizing DRIE parameters and 3 cycles of alternate oxidation of the trenches followed by oxide removal) to reduce the sidewall peak to valley roughness up to 50% [77]. In contrast, our work here uses only alternate cycles of oxidation and oxide removal and results in an increased roughness reduction.…”

“…Indeed, this is one of the key reasons why the trench-based process was selected for our micro-coils: since it is buried in the substrate it provides excellent planarity, thus enabling easy subsequent processing of other devices in the wafer (even on top of it after the Cu filling) and excellent thermal dissipation thus allowing the injection of large currents to generate stronger magnetic fields [20,21]. Even when compared with reports that used the same procedure of alternate oxidation and oxide etch cycles [75][76][77], our work not only provides a detailed analysis of the process steps but also shows better performance. A full comparison of our work with these previous reports is presented in Table 5.4.…”

“…For the lower portion of the trench Le et al did a 'post-DRIE' alternate oxidation and oxide etching cycles [77] to reduce the scalloping. In contrast, we did not modify any DRIE parameters and relied exclusively on the oxidation+oxide removal cycles to achieve a superior roughness reduction of 80%, compared to maximum 54% obtained by Le et al [77] only in the best case. It can also be noted from Table 5.4 that their initial peak-to-valley roughness was smaller than that in our work: max.…”