Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

Abstract

The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 • C in windows of patterned wafers are rough, we have first of all studied the 600 • C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 • C down to 600 • C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 • C and 725 • C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 • C on (1 0 0) or at 600 • C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5-3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were notably obtained for the lateral etching of the (1 1 0) and (1 0 0) SiGe sacrificial layers (thanks to a CF 4 -based dry plasma), with no anisotropy. Significant hole mobility gains (electron mobility loss) compared to the universal Si(1 0 0)/SiO 2 mobility were evidenced in long, narrow (L = 10 μm; W = 0.08 μm) 'bulk-like' epitaxial Si(1 1 0) L-SOI devices (i.e. with SiGe still present under most of the Si channel). The gain (the loss) monotonically increased from 120% (11%) up to 246% (58%) when moving away from the [0 0 1] direction toward the [1 −1 0] direction (not reached, however: at most at 60 • to [0 0 1]). Vastly improved hole transport properties (a factor of 2 On current increase) were evidenced in short dimensions L-SOI devices (L = 0.35 μm; W = 0.08 μm) when switching from (1 0 0) surfaces with 1 1 0 conduction channels to (1 1 0) surfaces with a [0 0 1] propagation direction for the holes.

Selective epitaxial growth of Ge(110) in trenches using the aspect ratio trapping technique

“…6). Such a (1 1 0) surface roughening by HCl has also been noticed at 675 1C for a 210 nm deep recess of Si windows [26]. We have plotted the rms roughness and Z range values corresponding to the different Si areas recessed at 750 1C in Fig.…”

“…Such a (1 1 0) surface roughening by HCl can be deleterious to the planarity of thin, pseudomorphic layers selectively grown in recessed areas, as shown in Ref. [26]. Here, given that we have investigated the growth of rather thick, relaxed Ge(1 1 0) layers with heavily defective Si substrate/Ge epilayer interfaces (due to the large lattice mismatch), this surface roughening is not so critical.…”

“…750 1C) than the one used in Ref. [26] to etch several tens of nm of Si in the windows of Si(1 1 0) patterned areas (i.e. 675 1C), in order to obtain several hundreds of nm deep Si(1 1 0) recesses.…”

HCl Selective Etching of SiGe versus Si in Stacks Grown on (110)

“…Thermal budget minimization is indeed a must, as (110) SiGe / Si heterostructures are more prone to plastic relaxation than (100) stacks (see Ref. (13) and references therein).…”

“…We have recently highlighted the promises of (110) L-SOI p-type MOSFETs (13). Such device architectures call upon several rather specific epitaxy and etch steps (14), which are surface orientation dependant (13), (15): (i) the gaseous HCl etch of Si in the active area (in order to avoid subsequent faceting), (ii) the Selective Epitaxial Growth (SEG) of {SiGe / Si} stacks with individual layer thickness in the 10 to 20 nm range and (iii) the SEG of Si Raised Sources and Drains (after the HfO 2 / TiN / poly-Si gate stack deposition and patterning). The Ge concentration of the SiGe sacrificial layer under the Si layer (which is the conduction layer of charge carriers) should be superior or equal to 20% in order to obtain a good lateral SiGe versus Si selective etch.…”